Architecture optimization methodology for dynamically reconfigurable stream processors

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During the last decade a real-time processing of data-streams has become the one of the major applications of high-performance computers (e.g. digital audio and video broadcasting, multimedia, machine vision, wireless communication and many other). Existing approaches are based on processors with fixed architecture: Application Specific Processors (ASP) or Application Specific Integrated circuits (ASIC). Platforms based on programmable processors are limited by performance due to sequential nature of computation. Platforms based on ASICs can provide the highest processing speed but due to the lack of flexibility no modification or fault recovery is possible. On the other hand, a recent progress in Field Programmable Gate Array (FPGA) technology has allowed a development of Dynamically Reconfigurable Stream Processors (DRSP), which may provide flexibility similar to programmable processors and processing speed close to ASIC based systems. However, the major problem with DRSP is keeping a high cost-efficiency by run-time optimization of its architecture to variation of the algorithms and data-stream structure of a workload. Another problem of DRSP based on SRAM FPGA devices is necessity of run-time self-recovery from hardware faults in the data-paths. Thus, the major problem in implementation of the concept of DRSP is lack of run-time architecture optimization mechanisms built-in to the system. These mechanisms should be able to reconfigure the stream-processing data-paths according to the algorithm / stream variations to keep the performance and cost-performance parameters on required level. Therefore, the proposed research seeks to achieve the following objectives: i) develop the high-level synthesis methodology for optimization of deep pipelined data-paths on the base of partially reconfigurable FPGAs; ii) develop algorithms and procedures for run-time selection of the close-to-optimal variant of architecture in multi-parametric design space; iii) investigate the cost-effectiveness of the developed methodology on experimental FPGA-based platform and iv) develop the self-restoration mechanisms for run-time mitigation of the transient (e.g. SEU) and permanent hardware faults.