Architecture optimization methodology for dynamically reconfigurable stream processors

在过去的十年中，数据流的实时处理已经成为高性能计算机(例如，数字音频和视频广播、多媒体、机器视觉、无线通信等)的主要应用之一。现有的方法基于具有固定体系结构的处理器：专用处理器(ASP)或专用集成电路(ASIC)。由于计算的顺序性质，基于可编程处理器的平台的性能受到限制。基于ASIC的平台可以提供最高的处理速度，但由于缺乏灵活性，无法进行任何修改或故障恢复。另一方面，现场可编程门阵列(现场可编程门阵列)技术的最新进展使得动态可重构流处理器(DRSP)的发展成为可能，其可以提供类似于可编程处理器的灵活性和接近基于ASIC的系统的处理速度。然而，DRSP的主要问题是通过对其体系结构的运行时优化来保持高的成本效率，以适应工作负载的算法和数据流结构的变化。基于SRAM器件的DRSP的另一个问题是需要在运行时从数据路径中的硬件故障中进行自我恢复。因此，实现DRSP概念的主要问题是缺乏内置到系统中的运行时体系结构优化机制。这些机制应该能够根据算法/流的变化重新配置流处理数据路径，以将性能和性价比参数保持在所需的水平。因此，本研究致力于实现以下目标：i)开发基于部分可重构的FPGA的深层流水线数据路径优化的高级综合方法；ii)开发多参数设计空间中运行时选择接近最优的体系结构变体的算法和程序；iii)在基于FPGA的实验平台上研究所开发的方法的成本效益；以及iv)开发用于运行时缓解瞬时(例如SEU)和永久性硬件故障的自恢复机制。

During the last decade a real-time processing of data-streams has become the one of the major applications of high-performance computers (e.g. digital audio and video broadcasting, multimedia, machine vision, wireless communication and many other). Existing approaches are based on processors with fixed architecture: Application Specific Processors (ASP) or Application Specific Integrated circuits (ASIC). Platforms based on programmable processors are limited by performance due to sequential nature of computation. Platforms based on ASICs can provide the highest processing speed but due to the lack of flexibility no modification or fault recovery is possible. On the other hand, a recent progress in Field Programmable Gate Array (FPGA) technology has allowed a development of Dynamically Reconfigurable Stream Processors (DRSP), which may provide flexibility similar to programmable processors and processing speed close to ASIC based systems. However, the major problem with DRSP is keeping a high cost-efficiency by run-time optimization of its architecture to variation of the algorithms and data-stream structure of a workload. Another problem of DRSP based on SRAM FPGA devices is necessity of run-time self-recovery from hardware faults in the data-paths. Thus, the major problem in implementation of the concept of DRSP is lack of run-time architecture optimization mechanisms built-in to the system. These mechanisms should be able to reconfigure the stream-processing data-paths according to the algorithm / stream variations to keep the performance and cost-performance parameters on required level. Therefore, the proposed research seeks to achieve the following objectives: i) develop the high-level synthesis methodology for optimization of deep pipelined data-paths on the base of partially reconfigurable FPGAs; ii) develop algorithms and procedures for run-time selection of the close-to-optimal variant of architecture in multi-parametric design space; iii) investigate the cost-effectiveness of the developed methodology on experimental FPGA-based platform and iv) develop the self-restoration mechanisms for run-time mitigation of the transient (e.g. SEU) and permanent hardware faults.