Collaborative Research: Low Power CMOS Circuits and Systems for Next Generation Wireless Information Technology

合作研究：下一代无线信息技术的低功耗 CMOS 电路和系统

• 批准号: 0219338
• 负责人: Eugene John
• 金额: $ 17.56万
• 依托单位: University of Texas at San Antonio
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2002
• 资助国家: 美国
• 起止时间: 2002-09-01 至 2006-08-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=0219338&HistoricalAwards=false
• 关键词: Collaborative; Research; Low; Power; CMOS

There is a rapidly growing trend toward embedding wireless capability into a wide variety of information technology products; recently in the form of single chip transceivers, and in the future perhaps integrated on-chip with the main product function. These devices must have low power consumption to satisfy battery conservation and thermal considerations. Good receiver sensitivity and signal handling are also essential in a crowded radio frequency (RF) spectrum; however, this requirement conflicts with low power circuit design. We propose to develop low power CMOS circuits that improve the trade-off between power consumption and RF performance. Current CMOS low noise amplifiers (LNA) have noise figures as low as 0.8 dB, input intercept points up to +18dBm, and power as low as 1.5 mW; however, these specifications cannot be obtained simultaneously. Likewise, CMOS mixers can meet demanding CDMA communications standards for linearity and noise figure, but only at high power cost.To address these problems we propose a number of strategies for (a) reducing power consumption for a given level of performance, and (b) allowing a dynamic trade-off of power versus RF performance. These trategies include: (1) reuse of amplifier stages at two different frequencies through reflex arrangements, thus reducing the number of high performance, high current stages required in receivers, (2) dynamically controlled positive feedback and bias in LNA stages, to allow power, signal handling, and noise figure to be traded off based on signal strength and interference, and (3) integration of charge pumps into individual drain supplies, to optimize the voltage for RF-critical stages while allowing the non-critical portions of a CMOS chip to operate at low voltage.Successful implementation will lead to improved range and life for wireless sensors, more reliable communications under adverse interference conditions, and ultimately to wider application of information technology in industry and science.

将无线功能嵌入到各种信息技术产品中的趋势正在迅速增长;最近是以单芯片收发器的形式，未来可能是与主要产品功能集成在芯片上。 这些设备必须具有低功耗，以满足电池保护和热考虑。 在拥挤的射频（RF）频谱中，良好的接收器灵敏度和信号处理也是必不可少的;然而，这一要求与低功耗电路设计相冲突。 我们建议开发低功耗CMOS电路，提高功耗和RF性能之间的权衡。 目前的CMOS低噪声放大器（LNA）的噪声系数低至0.8 dB，输入截点高达+18 dBm，功耗低至1.5 mW;然而，这些规格无法同时获得。 同样地，CMOS混频器可以满足CDMA通信标准对线性度和噪声系数的要求，但需要高功耗。为了解决这些问题，我们提出了一些策略：（a）在给定的性能水平下降低功耗，（B）允许功率与RF性能的动态权衡。 这些策略包括：（1）通过反射布置在两个不同频率处重复使用放大器级，从而减少接收器中所需的高性能、高电流级的数量，（2）动态控制LNA级中的正反馈和偏置，以允许基于信号强度和干扰来折衷功率、信号处理和噪声系数，以及（3）将电荷泵集成到各个漏极电源中，优化射频关键级的电压，同时允许CMOS芯片的非关键部分在低电压下工作。成功的实施将导致无线传感器的范围和寿命的改善，在不利的干扰条件下更可靠的通信，并最终在工业和科学中更广泛地应用信息技术。