CISE Research Resources: Reconfigurable Multi-Node Wireless Communication Testbed

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EIA 0224410PI(s): Wong, Tan F. Fang, Yuguang; Shea, John M.Institution: University of Florida Title: CISE RR: Reconfigurable Multi-Node Wireless Communication Testbed This proposal, developing a real-time wireless communication testbed of six reconfigurable transceiver nodes that operate in the 900MHz or 2.4GHz ISM band, enables conducting experiments on network protocols and communications techniques. Performing real-time experiments over real-life wireless communication channels, the infrastructure enables three projects.Collaborative Communications,Wireless Medium Access Control Protocol Design and Experiments, andReliability-Based Hybrid ARQ.The first project concerns collaborative transmission and reception among multiple nodes in a wireless network. Techniques of distributed space-time coding and distributed and iterative decoding will be employed respectively to achieve transmit and receive diversity. The second project uses the test-bed to test new medium access control (MAC) protocols that employ a set of back-off algorithms designed to avoid potential "future" collisions and reduce the percentage of idle slots. These MAC protocols have the advantage of fast collision resolution and hence give much higher throughput. The last project develops and investigates a new hybrid automatic repeat request (ARQ) scheme that can take advantage of reliability estimates generated by soft-input, soft-output (SISO) decoders. This ARQ scheme transmits additional information for the unreliable bits, and this information is used to do additional decoding. The test-bed will be utilized to perform real-time experiments on a real-life channel to examine the throughput and delay performance of this ARQ scheme, which can be evaluated via simulations otherwise.On the educational side, the platform provides integrated design training to undergraduate students. Conducting simulation studies on algorithms developed on the research projects, students will employ the test-bed to perform off-line experiments over a real communication channel to identify possible weaknesses of the algorithms developed based on theoretical models and then fine tune the algorithms to produce a real-time FPGA implementation.