CAREER: A Framework for Addressing Some Fundamental Challenges in Deeply Scaled CMOS Circuit Design

职业生涯：解决深度缩放 CMOS 电路设计中一些基本挑战的框架

• 批准号: 0238572
• 负责人: Borivoje Nikolic
• 金额: $ 40万
• 依托单位: University of California-Berkeley
• 依托单位国家: 美国
• 项目类别: Continuing Grant
• 财政年份: 2003
• 资助国家: 美国
• 起止时间: 2003-02-15 至 2008-01-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=0238572&HistoricalAwards=false
• 关键词: CAREER; Framework; Addressing; Some; Fundamental

Intellectual MeritDesign in power-limited scaling era. This proposal presents a general framework of minimization of power and energy in digital CMOS integrated circuits. This proposal presents a framework for designing digital circuits to either minimize power/energy dissipation for given performance or maximize the performance under power/energy constraints. The problem is defined at the circuit level, but is also expanded to include the device, microarchitecture and system levels.This framework will be used in designing signal processing blocks for communications and storage systems. The particular applications targeted are iterative decoders for turbo and low-density parity check decoding.Broader ImpactsThe broader impacts of this proposed project are twofold: 1) to widen the education in digital integrated circuits including power, energy, as well as robustness as key determining variables within digital integrated circuit designs and 2) to include these areas within the revised edition of a widely used textbook in Digital Integrated Circuit. My education plans aim at providing a solid analytical background and design intuition for our students in the design of digital circuits and systems.

智能优化设计在功率受限的缩放时代。该方案提出了一个数字CMOS集成电路功耗和能量最小化的总体框架。该建议提出了一个数字电路设计的框架，以最大限度地减少功率/能量耗散给定的性能或最大限度地提高性能下的功率/能量约束。这个问题是在电路级定义的，但也扩展到包括设备，微体系结构和系统级。这个框架将用于设计通信和存储系统的信号处理模块。针对的特定应用是用于turbo和低密度奇偶校验解码的迭代解码器。更广泛的影响这个拟议项目的更广泛的影响是双重的：1）扩大数字集成电路教育，包括电力，能源，以及鲁棒性作为数字集成电路设计中的关键决定变量，以及2）将这些领域包括在广泛使用的数字集成电路教科书的修订版中。我的教育计划旨在为我们的学生在数字电路和系统设计方面提供坚实的分析背景和设计直觉。