CAREER: A Framework for Addressing Some Fundamental Challenges in Deeply Scaled CMOS Circuit Design

有限功率扩展时代的智能价值设计。该方案提出了一种在数字cmos集成电路中最小化功耗的一般框架。该方案提出了一种设计数字电路的框架，既可以在给定的性能下最小化功耗/能量消耗，也可以在功率/能量约束下最大化性能。这个问题是在电路级定义的，但也扩展到包括设备、微体系结构和系统级。该框架将用于设计通信和存储系统的信号处理块。具体的应用是用于Turbo和低密度奇偶校验译码的迭代译码。广泛的影响这个拟议的项目的更广泛的影响是两方面的：1)扩大数字集成电路的教育，包括功率、能量以及稳健性，作为数字集成电路设计中的关键决定变量；2)将这些领域纳入广泛使用的数字集成电路教科书的修订版中。我的教育计划旨在为我们的学生提供坚实的分析背景和设计直觉，使他们能够设计数字电路和系统。

Intellectual MeritDesign in power-limited scaling era. This proposal presents a general framework of minimization of power and energy in digital CMOS integrated circuits. This proposal presents a framework for designing digital circuits to either minimize power/energy dissipation for given performance or maximize the performance under power/energy constraints. The problem is defined at the circuit level, but is also expanded to include the device, microarchitecture and system levels.This framework will be used in designing signal processing blocks for communications and storage systems. The particular applications targeted are iterative decoders for turbo and low-density parity check decoding.Broader ImpactsThe broader impacts of this proposed project are twofold: 1) to widen the education in digital integrated circuits including power, energy, as well as robustness as key determining variables within digital integrated circuit designs and 2) to include these areas within the revised edition of a widely used textbook in Digital Integrated Circuit. My education plans aim at providing a solid analytical background and design intuition for our students in the design of digital circuits and systems.