A Hardware/Software Framework for Managing On-Chip Communication Latency

管理片上通信延迟的硬件/软件框架在现代计算系统中，性能和正确性之间存在内在的张力。处理器和编译器正变得越来越复杂，以保持通常以摩尔定律为特征的性能增长。这种复杂性使得确保这些系统可靠运行具有极大的挑战性和成本。在这个项目中，我们探索一种执行范例，它通过同时执行程序二进制文件的两个版本的执行来解耦性能和正确性：一个负责性能，一个负责正确性。性能执行负责以很高的可能性但不保证正确性快速执行程序；缺乏正确性保证使程序和硬件都有显著的优化机会，而不会产生验证开销。性能执行的结果可用于并行化正确性执行，其负责更新用户可见(架构化)状态。并行化使一组简单的处理器可以使用程序的未优化版本来执行正确的执行。除了降低验证的复杂性外，拟议的执行范例似乎还具有提高性能和降低功耗的潜力。

A Hardware/Software Framework for Managing On-Chip Communication LatencyIn modern computing systems, there is an inherent tension between performance and correctness. Processors and compilers are becoming increasingly complicated to maintain the performance growth often characterized by Moore's Law. This complexity makes it very challenging and costly to ensure these systems operate reliably. In this project, we explore an execution paradigm that decouples performance and correctness by simultaneously performing executions of two versions of a program's binary: one responsible for performance and one for correctness. The performance execution is responsible for executing the program quickly with a high likelihood, but no guarantee, of correctness; the lack of correctness guarantees enables significant optimization opportunities of both the program and the hardware, without overheads of verification. The results of the performance execution can be used to parallelize the correctness execution, which is responsible for updating user-visible (architected) state. Parallelization enables the correctness execution to be performed by a collection of simple processors using an unoptimized version of the program. In addition to reducing verification complexity, the proposed execution paradigm appears to have potential to improve performance and reduce power consumption.