A Hardware/Software Framework for Managing On-Chip Communication Latency

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A Hardware/Software Framework for Managing On-Chip Communication LatencyIn modern computing systems, there is an inherent tension between performance and correctness. Processors and compilers are becoming increasingly complicated to maintain the performance growth often characterized by Moore's Law. This complexity makes it very challenging and costly to ensure these systems operate reliably. In this project, we explore an execution paradigm that decouples performance and correctness by simultaneously performing executions of two versions of a program's binary: one responsible for performance and one for correctness. The performance execution is responsible for executing the program quickly with a high likelihood, but no guarantee, of correctness; the lack of correctness guarantees enables significant optimization opportunities of both the program and the hardware, without overheads of verification. The results of the performance execution can be used to parallelize the correctness execution, which is responsible for updating user-visible (architected) state. Parallelization enables the correctness execution to be performed by a collection of simple processors using an unoptimized version of the program. In addition to reducing verification complexity, the proposed execution paradigm appears to have potential to improve performance and reduce power consumption.