A Hardware/Software Framework for Managing On-Chip Communication Latency

用于管理片上通信延迟的硬件/软件框架在现代计算系统中，性能和正确性之间存在固有的紧张关系。 为了保持摩尔定律所表征的性能增长，处理器和编译器变得越来越复杂。 这种复杂性使得确保这些系统可靠运行非常具有挑战性且成本高昂。 在这个项目中，我们探索了一种执行范例，通过同时执行程序二进制文件的两个版本来解耦性能和正确性：一个负责性能，一个负责正确性。 性能执行负责快速执行程序，并且有很高的可能性，但不能保证正确性；缺乏正确性保证使得程序和硬件都有显着的优化机会，而无需验证的开销。性能执行的结果可用于并行化正确性执行，其负责更新用户可见（架构）状态。并行化使得一组简单处理器使用程序的未优化版本来执行正确性执行。 除了降低验证复杂性之外，所提出的执行范例似乎还具有提高性能和降低功耗的潜力。

A Hardware/Software Framework for Managing On-Chip Communication LatencyIn modern computing systems, there is an inherent tension between performance and correctness. Processors and compilers are becoming increasingly complicated to maintain the performance growth often characterized by Moore's Law. This complexity makes it very challenging and costly to ensure these systems operate reliably. In this project, we explore an execution paradigm that decouples performance and correctness by simultaneously performing executions of two versions of a program's binary: one responsible for performance and one for correctness. The performance execution is responsible for executing the program quickly with a high likelihood, but no guarantee, of correctness; the lack of correctness guarantees enables significant optimization opportunities of both the program and the hardware, without overheads of verification. The results of the performance execution can be used to parallelize the correctness execution, which is responsible for updating user-visible (architected) state. Parallelization enables the correctness execution to be performed by a collection of simple processors using an unoptimized version of the program. In addition to reducing verification complexity, the proposed execution paradigm appears to have potential to improve performance and reduce power consumption.