Phase-Directed Architecture Optimization and Simulation

面向阶段的体系结构优化和仿真程序的执行通常表现为时变行为，其中获得应用程序峰值性能所需的体系结构资源可能随时间变化很大。我们发现这种随时间变化的行为对于大多数应用程序具有重复的模式，这允许将程序的执行分解为阶段，然后我们可以为每个阶段定制程序的执行。这个建议集中于开发有效的运行时架构来捕获和预测阶段信息。我们将研究为电力和能源架构优化创建阶段跟踪和预测架构，以及根据跟踪缓存优化的阶段执行硬件代码专门化。基于特定的应用程序，通过动态地重新划分处理器中的许多组件（例如，缓存、发行和解码宽度、分支预测器），或者根据应用程序中看到的相位行为，有选择地使用这些组件的不同实现，可以潜在地节省能耗。此外，将针对不同阶段执行跟踪缓存编译器优化，以利用基于阶段的行为。对于更广泛的影响，我们的相位分类算法将允许研究人员有效地识别、分类和预测程序中的基于相位的行为，并使用这些信息来指导他们基于相位的硬件、编译器和操作系统的研究。

Phase-Directed Architecture Optimization and SimulationA program's execution typically exhibits time-varying behavior, where architecture resources needed to obtain peak performance for the application can vary significantly over time. We have found that this time-varying behavior has a repetitive pattern for most applications, which allows a program's execution to be broken up into phases, and we can then tailor a program's execution to each phase.This proposal concentrates on developing efficient run-time architectures to capture and predict phase information. We will examine creating phase tracking and prediction architectures for power and energy architecture optimizations as well as to perform hardware code specialization based on phases for trace cache optimizations. Energy consumption can potentially be saved by dynamically re-partitioning many components in a processor (e.g., caches, issue and decode width, branch predictors) on an application specific basis, or selectively using different implementations of these components based upon the phase behavior seen in an application. In addition, trace cache compiler optimizations will be performed for different phases to exploit phase-based behavior.For broader impact, our phase-classification algorithms will allow researchers to efficiently identify, classify, and predict phase-based behavior in programs and use this information to guide their phase-based hardware, compiler, and operating system research.