ITR: Concurrent Electro-Thermal Modeling of Ultra-Scaled MOS Technologies

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In recent years, there has been continuous miniaturization of microelectronic devices and circuits. Typical channel lengths in electronic devices, currently at 180 nm, are expected to fall to 70 nm by the year 2008 and new devices in the 3-40 nm range have already been fabricated in research laboratories. Despite drops in supply voltage, power dissipation in emerging transistor designs is expected to reach 160 W per chip by the end of this decade. Emerging technologies, such as silicon-on-insulator (SOI) FETs, face severely increased self-heating because of the thermally insulating properties of the chip design, and thermally-induced failures are expected to increase. This proposal seeks to explore computationally the coupled electro-thermal behavior of microelectronic devices. Though channel scales ranging from 10-180 nm will be studied to build a complete picture, the emphasis of the proposal is on understanding thermal behavior at the smaller scales. The proposed work will explore the influence of important micro-scale thermal phenomena such as phonon boundary scattering, small heat-source effects due to ballistic phonon transport in the hot spot, and phonon confinement effects, which substantially alter phonon dispersion curves and decrease phonon group velocities. Models based on both molecular dynamics as well as the Boltzmann transport equation will be developed, with electron-phonon interaction being computed by the full-band Monte Carlo simulator MOCA. Finally, these phonon transport and heat generation models will be coupled to Fourier conduction models for other device structures to understand the thermal behavior of emerging ultra-scaled devices. This proposal was submitted in response to NSF 02-168 Information Technology Research, in the "Small" category. The award has been funded by the Thermal Transport and Thermal Processing Program of the Chemical and Transport Systems Division.