ITR: Synchroscalar: Exploiting Synchronized Clock Domains for Energy Efficient Multirate Embedded Computation

ITR：同步标量：利用同步时钟域实现节能多速率嵌入式计算

• 批准号: 0312837
• 负责人: Frederic Chong
• 金额: $ 30万
• 依托单位: University of California-Davis
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2003
• 资助国家: 美国
• 起止时间: 2003-08-15 至 2007-07-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=0312837&HistoricalAwards=false
• 关键词: ITR; Synchroscalar; Exploiting; Synchronized; Clock

ChongITR: Synchroscalar, Exploiting Synchronized Clock Domains for EnergyEfficient Multirate Embedded SystemsAbstractUbiquitous computation and communication devices will dominate the social and economic landscape of the new millennium. As the functionality of these devices evolve, current microprocessor designs cannot keep up with the battery life and the performance requirements. We propose to address this problem with a novel microprocessor design that uses a combination of two approaches. First, we break the work into many parallel pieces to increase performance. Second, to save power, we run each piece at the minimal speed necessary to achieve the quality of communication desired. Specifically, we propose the Synchroscalar architecture, a two-dimensional mesh of processing tiles in which each column forms a separate clock and voltage domain. Clock frequencies are related by a rational factor, which will be exploited to schedule data transfers between different clock domains without incurring the overhead of asynchronous communication between clock boundaries, yet retaining the benefits of optimal clocking for each column. This organization gives us the many of the energy advantages of asynchronous systems while maintaining the simplicity of a synchronous system.The success of these approaches will significantly increase the impact of information technology on the nation, enabling many "wired" applications to become wireless and mobile.

ChongITR：同步标量，利用同步时钟域的节能多速率嵌入式系统摘要无处不在的计算和通信设备将主导新千年的社会和经济景观。 随着这些设备功能的发展，当前的微处理器设计无法跟上电池寿命和性能要求。我们建议解决这个问题，一个新的微处理器设计，使用两种方法的组合。首先，我们将工作分成许多并行的部分以提高性能。 其次，为了节省电力，我们以最低速度运行每个片段，以实现所需的通信质量。 具体来说，我们提出了Synchroscalar架构，这是一个处理模块的二维网格，其中每列形成一个单独的时钟和电压域。 时钟频率与有理因子相关，该有理因子将被利用来调度不同时钟域之间的数据传输，而不会引起时钟边界之间的异步通信的开销，同时保留每列的最佳时钟的优点。 这种组织给了我们异步系统的许多能量优势，同时保持了同步系统的简单性。这些方法的成功将大大增加信息技术对国家的影响，使许多“有线”应用成为无线和移动的。