CAREER: Care and Feeding of High-Performance Processors with Reconfigurable Memory Systems

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*** 9733475 Chong Microprocessor performance continues to increase faster than memory performance, so that computer systems face a memory bottleneck. The goal of this project is to distribute logic within memory systems so that some computations can be performed in the memory system without transferring data to the processor. By fabricating field-programmable gate arrays and memory on the same chip, computations for fine-grained data manipulation can be distributed to the memory system at run time to speed up specific applications.A crucial research issue in such a design is the partitioning of computations between high-performance processors and the distributed logic. This project is investigating this partitioning on a range of appilications, including integer programming for compiler register allocation, filters for image and video editing, internet routing, graph matching for intrusion detection, and protein sequence matching. Educational plans include the updating of several existing courses in computer architecture, the development of new courses in reconfigurable computing, and the incorporation of undergraduate research into the project. Expected outcomes of this project include a methodology for designing reconfigurable memory systems and using them in computations, an infrastructure of simulation tools and hardware prototypes, students trained in applications-driven system design, and web-based educational software to support collaborative projects in computer architecture. ***