SBIR Phase I: Non-Contact/Zero-Stress Surface Polishing Process for Copper/Low Dielectric Constant Semiconductors

SBIR 第一阶段：铜/低介电常数半导体的非接触/零应力表面抛光工艺

• 批准号: 0319170
• 负责人: E. Jennings Taylor
• 金额: $ 10万
• 依托单位: FARADAY TECHNOLOGY, INC
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2003
• 资助国家: 美国
• 起止时间: 2003-07-01 至 2003-12-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=0319170&HistoricalAwards=false
• 关键词: SBIR; Phase; Non; Contact; Zero

This Small Business Innovation Research (SBIR) Phase I project will develop a novel, non-contact/stress-free polishing method for planarization of copper (Cu)/low-k (dielectric constant) interconnects required for the fabrication of nanochip integrated circuits (IC). A currently used process step, chemical-mechanical-polishing (CMP), is adequate for copper/silicon dioxide interconnects. However, the reduced mechanical strength of the low-k dielectric materials required for nanochips (100nm and smaller interconnects) renders CMP incompatible with future IC interconnects. The proposed method utilizes pulsed electrolysis to effect complete electrochemical removal of copper overplate beginning from the center of the wafer and moving outward where electrical contact is provided. The Phase I research issues include: 1) complete removal of copper overplate, i.e. no copper islands remaining, and 2) no damage to the interconnect, i.e. filled and not eroded or dished. Real-time video feed observation and post process FIB-SEM analysis will be conducted to validate process feasibility. Analytical work will be conducted to establish a theoretical basis for the proposed electrochemical process.Commercially, the non-contact/stress-free polishing method will find application to Cu/low-k interconnects required for integrated circuits down to the 35nm mode. Additional applications of the process include micro-electro-mechanical systems (MEMS) and nano-electro-mechanical systems (NEMS). The industry addressed semiconductor is an important aspect of the US commercial economy. The result of the research will lead to a marketable manufacturing process/manufacturing tool in the form of an electrochemical module incorporating the non-contact/zero stress polishing process.

该小型企业创新研究（SBIR）第一阶段项目将开发一种新颖的非接触/无应力抛光方法，用于纳米芯片集成电路（IC）制造所需的铜（Cu）/低k（介电常数）互连的平面化。 目前使用的工艺步骤，化学机械抛光（CMP），是足够的铜/二氧化硅互连。 然而，纳米芯片（100 nm和更小的互连）所需的低k电介质材料的机械强度降低使得CMP与未来的IC互连不兼容。 所提出的方法利用脉冲电解来实现从晶片的中心开始并在提供电接触的地方向外移动的铜电镀的完全电化学去除。 第一阶段的研究问题包括：1）完全去除铜电镀，即没有铜岛剩余，和2）没有损坏的互连，即填充和不侵蚀或凹陷。 将进行实时视频进料观察和处理后FIB-SEM分析，以验证工艺可行性。 在商业上，非接触/无应力抛光方法将应用于低至35 nm模式的集成电路所需的Cu/low-k互连。 该工艺的其他应用包括微机电系统（MEMS）和纳米机电系统（NEMS）。 半导体工业是美国商业经济的一个重要方面。 研究的结果将导致一个适销对路的制造工艺/制造工具的电化学模块的形式纳入非接触/零应力抛光过程。