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SBIR Phase I: Non-Contact/Zero-Stress Surface Polishing Process for Copper/Low Dielectric Constant Semiconductors

SBIR Phase I: Non-Contact/Zero-Stress Surface Polishing Process for Copper/Low Dielectric Constant Semiconductors
SBIR 第一阶段:铜/低介电常数半导体的非接触/零应力表面抛光工艺
批准号:
0319170
负责人:
E. Jennings Taylor
金额:
$10.0万
依托单位:
依托单位国家:
美国
项目类别:
Standard Grant
财政年份:
2003
资助国家:
美国
项目状态:
已结题
起止时间:
2003-07-01 至 2003-12-31

项目摘要

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中文摘要
翻译
这个小型企业创新研究(SBIR)第一阶段项目将开发一种新的、非接触/无应力抛光方法,用于纳米芯片集成电路(IC)制造所需的铜(Cu)/低k(介电常数)互连的平面化。目前使用的化学-机械-抛光(CMP)工艺步骤适用于铜/二氧化硅互连。然而,纳米芯片(100nm及更小的互连)所需的低k介电材料的机械强度降低使得CMP与未来的IC互连不兼容。所提出的方法利用脉冲电解来实现从晶圆片中心开始并向提供电接触的地方向外移动的铜覆盖板的完全电化学去除。第一阶段的研究问题包括:1)完全去除铜覆盖板,即没有铜岛,以及2)互连不损坏,即填充而不侵蚀或盘状。将进行实时视频馈送观察和过程后FIB-SEM分析以验证工艺可行性。将进行分析工作,为提出的电化学过程建立理论基础。在商业上,非接触/无应力抛光方法将应用于集成电路所需的Cu/低k互连,直至35nm模式。该工艺的其他应用包括微机电系统(MEMS)和纳米机电系统(NEMS)。半导体行业是美国商业经济的一个重要方面。这项研究的结果将导致一种市场化的制造工艺/制造工具,其形式是包含非接触/零应力抛光工艺的电化学模块。
英文摘要
This Small Business Innovation Research (SBIR) Phase I project will develop a novel, non-contact/stress-free polishing method for planarization of copper (Cu)/low-k (dielectric constant) interconnects required for the fabrication of nanochip integrated circuits (IC). A currently used process step, chemical-mechanical-polishing (CMP), is adequate for copper/silicon dioxide interconnects. However, the reduced mechanical strength of the low-k dielectric materials required for nanochips (100nm and smaller interconnects) renders CMP incompatible with future IC interconnects. The proposed method utilizes pulsed electrolysis to effect complete electrochemical removal of copper overplate beginning from the center of the wafer and moving outward where electrical contact is provided. The Phase I research issues include: 1) complete removal of copper overplate, i.e. no copper islands remaining, and 2) no damage to the interconnect, i.e. filled and not eroded or dished. Real-time video feed observation and post process FIB-SEM analysis will be conducted to validate process feasibility. Analytical work will be conducted to establish a theoretical basis for the proposed electrochemical process.Commercially, the non-contact/stress-free polishing method will find application to Cu/low-k interconnects required for integrated circuits down to the 35nm mode. Additional applications of the process include micro-electro-mechanical systems (MEMS) and nano-electro-mechanical systems (NEMS). The industry addressed semiconductor is an important aspect of the US commercial economy. The result of the research will lead to a marketable manufacturing process/manufacturing tool in the form of an electrochemical module incorporating the non-contact/zero stress polishing process.
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