SBIR/STTR Phase II: A Low Cost Semiconductor Metallization-Planarization Process

这个小企业创新研究第二阶段项目将建立一种新型电介质调平技术的市场需求，并通过合资企业将该技术推向市场。第二阶段的具体目标是：8英寸晶圆上电介导工艺的放大与演示，2。开发用于特征尺寸1-5至0.17微米及以下的过程库；“概念验证”电镀工具的设计。采用电介导工艺的电镀工具的初步概念设计将由外部公司执行。与项目相关的可持续竞争优势是成本。与最先进的铜金属化工艺相比，通过减少铜废浆，最小的覆盖层将消除或最大限度地减少对化学/机械刨平（CMP）的需求。这反过来又会消除相关的控制、环境和成本问题。

This Small Business Innovation Research Phase II Project will establish market demand for a novel electrically mediated leveling technology and position the technology for market launch via a joint venture. The specific Phase II objectives are: 1. Scale-up and demonstration of the electrically mediated process on eight inch wafers, 2. Development of a process library for feature sizes 1-5 down to 0.17 microns, and lower, and 3. Design of a "proof of concept" plating tool. Preliminary concept design of a plating tool incorporating the electrically mediated process will be performed by an outside firm. The sustainable competitive advantage associated with the project for leveling is cost. Minimal overplate will eliminate or minimize the need for chemical/mechanical planarization (CMP) by reducing the copper waste slurry compared to the state-of-the-art copper metallization processes. This in turn would eliminate the associated control, environmental, and cost issues.