SGER: Evaluating Reliability of Defect Tolerant Architectures for Nanotechnology using Probabilistic Model Checking

SGER：使用概率模型检查评估纳米技术缺陷容忍架构的可靠性

• 批准号: 0340740
• 负责人: Sandeep Shukla
• 金额: $ 5万
• 依托单位: Virginia Polytechnic Institute and State University
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2003
• 资助国家: 美国
• 起止时间: 2003-07-01 至 2005-06-30
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=0340740&HistoricalAwards=false
• 关键词: SGER; Evaluating; Reliability; Defect; Tolerant

With the advances in silicon technology as predicted by Moore's law, we are already in deep sub-micron era of device feature size. Currently 90 nanometer (90 nm) is a reality, and very soon we will be in the tens of microns. The technology will then change drastically, with single electron transistors and such artifacts of nano-technology era. As a result, uncertainties about the device behaviors will be a common problem that engineers will have to deal with, in such miniscule quantum level of technology. Currently, while designing computer architecture components, engineers safely assume that the transistors and logic gates will behave as predicted by the theory. However, with uncertainties being rampant in nano-technology, one can only rely on the measures of the probability that a transistor will behave correctly, or a logic gate will function correctly. As a result, in order to implement a logic function and to depend on it with high degree of reliability, engineers will have to build redundancy in the design, such that if some of the gates fail, even then, the functional block will provide the correct functionality with very high degree of reliability. However, how to build redundancy for particular logic functions, and how much redundancy is enough, and at what level of redundancy, the reliability actually decreases, are questions to be answered by an engineering tool, before such redundancy is built into the system. Von Neumann looked at similar problems for logic gates since during his time, logic gates were built with valves which were quite unreliable. Information theorists also look at similar problems in terms of noise tolerance by logic functions. However, no tool exists for such evaluations, nor does a precise engineering methodology exist. This project aims at bringing in the novel technology of probabilistic model checking and create a methodology and tool set for evaluation of reliability for different alternate redundant architectures and compute reliability measures before the design is built to steer the engineers in the right directions. This work will help prepare computer engineers in building reliable functionalities on unreliable nano-substrates, given that material scientists can calibrate nano-materials for probability of failures. This work therefore will have great impact in the future computer engineering and logic design. Also it will help educate future engineers to face the nano era and build reliable computing infrastructures.

随着摩尔定律预言的硅技术的进步，我们已经进入了器件特征尺寸的深亚微米时代。目前90纳米（90 nm）是一个现实，很快我们将在几十微米。然后，随着单电子晶体管和纳米技术时代的人工制品的出现，该技术将发生巨大变化。因此，在如此微小的量子技术水平上，设备行为的不确定性将是工程师必须处理的一个常见问题。目前，在设计计算机架构组件时，工程师们安全地假设晶体管和逻辑门将按照理论预测的那样工作。然而，由于纳米技术中的不确定性猖獗，人们只能依赖于晶体管正确工作或逻辑门正确工作的概率的测量。因此，为了实现逻辑功能并以高度的可靠性依赖于它，工程师将不得不在设计中建立冗余，使得即使在某些门失效的情况下，功能块也将以非常高的可靠性提供正确的功能。然而，如何为特定的逻辑功能建立冗余，以及多少冗余是足够的，以及在什么水平的冗余下，可靠性实际上会降低，这些都是在将这种冗余建立到系统中之前要由工程工具回答的问题。冯诺依曼着眼于类似的问题，逻辑门，因为在他的时间，逻辑门是建立与阀门这是相当不可靠的。 信息理论家也从逻辑函数的噪声容忍度的角度来看待类似的问题。然而，目前还没有进行这种评估的工具，也没有精确的工程方法。该项目旨在引入概率模型检查的新技术，并创建一种方法和工具集，用于评估不同备用冗余架构的可靠性，并在设计之前计算可靠性措施，以引导工程师朝着正确的方向前进。这项工作将有助于计算机工程师在不可靠的纳米基板上构建可靠的功能，因为材料科学家可以校准纳米材料的故障概率。因此，这项工作将对未来的计算机工程和逻辑设计产生重大影响。 此外，它将有助于教育未来的工程师面对纳米时代，建立可靠的计算基础设施。