SGER: Evaluating Reliability of Defect Tolerant Architectures for Nanotechnology using Probabilistic Model Checking

SGER：使用概率模型检查评估纳米技术缺陷容忍架构的可靠性

• 批准号: 0340740
• 负责人: Sandeep Shukla
• 金额: $ 5万
• 依托单位: Virginia Polytechnic Institute and State University
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2003
• 资助国家: 美国
• 起止时间: 2003-07-01 至 2005-06-30
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=0340740&HistoricalAwards=false
• 关键词: SGER; Evaluating; Reliability; Defect; Tolerant

With the advances in silicon technology as predicted by Moore's law, we are already in deep sub-micron era of device feature size. Currently 90 nanometer (90 nm) is a reality, and very soon we will be in the tens of microns. The technology will then change drastically, with single electron transistors and such artifacts of nano-technology era. As a result, uncertainties about the device behaviors will be a common problem that engineers will have to deal with, in such miniscule quantum level of technology. Currently, while designing computer architecture components, engineers safely assume that the transistors and logic gates will behave as predicted by the theory. However, with uncertainties being rampant in nano-technology, one can only rely on the measures of the probability that a transistor will behave correctly, or a logic gate will function correctly. As a result, in order to implement a logic function and to depend on it with high degree of reliability, engineers will have to build redundancy in the design, such that if some of the gates fail, even then, the functional block will provide the correct functionality with very high degree of reliability. However, how to build redundancy for particular logic functions, and how much redundancy is enough, and at what level of redundancy, the reliability actually decreases, are questions to be answered by an engineering tool, before such redundancy is built into the system. Von Neumann looked at similar problems for logic gates since during his time, logic gates were built with valves which were quite unreliable. Information theorists also look at similar problems in terms of noise tolerance by logic functions. However, no tool exists for such evaluations, nor does a precise engineering methodology exist. This project aims at bringing in the novel technology of probabilistic model checking and create a methodology and tool set for evaluation of reliability for different alternate redundant architectures and compute reliability measures before the design is built to steer the engineers in the right directions. This work will help prepare computer engineers in building reliable functionalities on unreliable nano-substrates, given that material scientists can calibrate nano-materials for probability of failures. This work therefore will have great impact in the future computer engineering and logic design. Also it will help educate future engineers to face the nano era and build reliable computing infrastructures.

随着摩尔定律预测的硅技术的进步，我们已经处于设备功能大小的深度亚微米时代。目前，90纳米（90 nm）是现实，很快我们将处于数十万微米。然后，该技术将随着单电子晶体管和纳米技术时代的这种伪影发生巨大变化。结果，关于设备行为的不确定性将是工程师在这种微小的量子技术水平中必须处理的常见问题。当前，在设计计算机架构组件的同时，工程师安全地假设晶体管和逻辑门将按照理论的预测行为。但是，由于不确定性在纳米技术方面猖ramp，因此只能依靠晶体管行为正确的概率的度量，或者逻辑门将正常运行。结果，为了实现逻辑功能并具有高度的可靠性，工程师将不得不在设计中构建冗余，以便如果某些大门失败，即使到那时，功能块仍将提供具有很高可靠性的正确功能。但是，如何为特定的逻辑功能构建冗余，以及冗余的程度，以及在哪个级别的冗余，可靠性实际上降低的是工程工具要回答的问题，在内置到系统中之前。冯·诺伊曼（Von Neumann）在逻辑大门（Logic Gates）时期研究了类似的问题，因为在他的那段时间里，逻辑大门是用阀门建造的，这些阀非常不可靠。 信息理论家还通过逻辑函数来研究类似的问题。但是，没有用于此类评估的工具，也不存在精确的工程方法。该项目旨在引入概率模型检查的新技术，并创建一个方法和工具集，以评估不同替代冗余体系结构的可靠性，并在构建设计以将工程师转向正确方向之前的设计前。这项工作将有助于计算机工程师在不可靠的纳米材料上构建可靠的功能，因为物质科学家可以校准纳米材料以实现故障的可能性。因此，这项工作将对未来的计算机工程和逻辑设计产生重大影响。 这也将有助于教育未来的工程师面对纳米时代并建立可靠的计算基础架构。