Cooperative Hardware/Software Designs for Virtual Instruction Set Computers

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AbstractCooperative Hardware/Software Designs for virtual Instruction Set ComputersVikram S. AdveU. of Illinois, Urbana0429561This work proposes a class of cooperative compiler/microarchitecture techniques that can improve performance and reduce the complexity and power-consumption of general-purpose processors. The key feature of these proposed techniques is that they exploit a wide, implementation-specific instruction set interface between the compiler and the processor, enabled by the use of Virtual Instruction Set Computer (VISC) architecture.A VISC architecture is characterized by having two instructions sets - one which is exposed to software (the virtual ISA or V-ISA) and another which is actually implemented by hardware (the implementation ISA or I-ISA)-and a translator that is used to transparently emulate the first with the second. Because the I-ISA is never exposed to software (other than an implementation-specific translator that is logically part of the processor design) it can freely expose implementation specific microarchitectural details and interfaces without concerns for binary compatibility across implementations. It is this opportunity to architect an implementation-specific ISA and use it for cooperative compiler/microarchitecture techniques that is the central focus of this proposal.Two aspects of the proposed work differentiate it from previous work on software-exposed architectures. First, we are translating from a rich V-ISA layer that retains much of the high-level information present in the program's source code. We hypothesize that the availability of this information is fundamental in the translator's ability to transform the code to exploit the proposed mechanisms, and we will evaluate this hypothesis for the proposed techniques. Second, the proposed techniques are truly cooperative, in that the compiler can have full knowledge of implementation-specific details of the microarchitecture, and the microarchitecture can rely on information from and code generation constraints on the complier. This gives our designs full freedom to exploit the distinct and complimentary strengths of compilers and hardware; neither system is the other's subordinate. Whereas hardware can efficiently observe and respond to dynamic events and can cheaply speculate and validate that speculation, the compiler can perform global analysis to reduce and simplify the decisions the hardware has to make and to eliminate unnecessary speculation.Specifically, we proposed to develop cooperative compiler technology and microarchitectures that address critical challenges in modern general-purpose processors. For each of these challenges, we will explore one or two techniques (described in the proposal) that rely extensively on software interaction, and which would be impractical without the VISC approach.