Architectural Support for Effective User-Level Data Transport

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Architectural Support for Effective User-Level Data TransportAbstractThe objective of this project is to enable microprocessors to better utilize recent performance advances in I/O and networking. It seeks to enable next-generation I/O and networking services on general-purpose microprocessors by the addition of a subsystem consisting of multiple clusters of simple processors, and appropriate interconnects, to handle network and I/O traffic without making the central processor unit (CPU) core, or its operating system, an artificial bottleneck. The research activities will prototype, demonstrate and evaluate our proposed system though a combination hardware prototypes, software simulation and application development.The research directly addresses a critical problem common to all modern information technology systems: while commodity CPU and network performance have each independently seen dramatic performance improvements over the last decade, their combined use results in an inefficient system. In other workloads, modem CPUs achieve their promise on traditional computing workloads, and modern networking systems do the same for traditional communications tasks, but a combined system is unable to support emerging services (such as large-scale storage systems, content scanning systems and on-demand media) at the performance levels expected for such otherwise high-performance systems. The central problem lies in the hardware and software interfaces between the CPU and the network. Our proposed research aims to re-organize the CPU to better support high-performance networks and I/O and enable a proliferation of advanced network and I/O services on general-purpose commodity systems.