CSR--AES: Multiprocessor Chip for Modular Software

该项目将设计和评估一个新的架构和通用多处理器芯片的编程模型。 该芯片将包括8到16个处理器，每个处理器都是同时多线程组织，并具有超标量性能。内存模型将支持一个64位地址空间的1024位内存“块”，用于保存所有用户共享的程序和数据。活动块将被保持在片上完全关联的缓存单元中，并且当被新的活动块替换时被“分页"到片外存储器。 这个提议的一个独特之处在于，数据块被创建、初始化、访问和发布，但永远不会更新。其结果是系统中没有缓存一致性问题，实现存储器访问的安全性是直接的，并且存储器管理很容易在硬件中实现。应用程序编程将在Java编程语言中得到支持，受到限制，以便满足模块化软件组件的安全参数原则，并且隐式并行性可以是实现高水平并行处理性能的基础。要执行的工作包括实现一个周期准确的模拟建议的多处理器芯片，开发一个翻译器从Java字节码类文件的建议的多线程指令集，并评估几个代表性的应用程序的可编程性和性能。

The project will design and evaluate a novel architecture and programming model for a general purpose multiprocessor chip. The chip will include eight to sixteen processors, each of which is of simultaneous multithread organization and capable of superscalar performance. The memory model will support a 64-bit address space of 1024-bit "chunks" of memory used to hold programs and data shared by all users. Active chunks will be held in on-chip fully associative cache units, and ''paged'' to off-chip memory when replaced by newly active chunks. A unique feature of this proposal is that chunks of data are created, initialized, accessed, and released, but are never updated. The result is a system in which there is no cache consistency issue, implementing security of memory access is straightforward, and memory management is readily implemented in hardware. Application programming will be supported in the Java programming language, restricted so that the Secure Arguments principle for modular software components is satisfied, and implicit parallelism can be the basis for achieving high levels of parallel processing performance. The work to be performed includes implementing a cycle-accurate simulation of the proposed multiprocessor chip, developing a translator from Java bytecode class files to the proposed multithread instruction set, and evaluating programmability and performance for several representative applications.