SBIR Phase I: Hermetic Micropackaging Applying Wafer-Level and Chip-Scale Integration

这个小型企业创新研究第一阶段项目致力于MEMS/NEMS组件和系统的封装技术。采用晶片级和芯片级的新设计将允许对敏感结构进行密封封装，以及系统组件的简单、多功能电气、微流体、光学和热互连。该项目将展示一种封装电子元件的方法的可行性，该方法a)优化高频性能；b)最大限度地降低成本；c)在封装期间和使用寿命期间保护元件的完整性；d)保持应用灵活性。将演示基本工艺步骤，并使用专利技术为光学元件的晶片级芯片级封装开发原型，这些技术用于预薄晶片的临时晶片粘合；通过衬底形成通孔，以及通孔的绝缘和金属化；以及通过焊接或其他方法连接。拟议的封装技术允许将各种设备放置在一个微型密封腔中，具有在使用寿命内保持真空的规定。此外，与喷墨打印方法相结合，单孔设计可适用于流体、光学或散热。晶片级和芯片规模的封装具有小型化、降低成本以及增强性能和可靠性的关键优势。事实上，这些都是大多数半导体行业的历史和未来驱动因素。除了主流的半导体应用，该方法还为惯性级导航仪器等设备提供了独特的解决方案，在这些设备中，性能和可靠性的增强可能是至关重要的。

This Small Business Innovation Research Phase I project addresses packaging techniques for MEMS/NEMS components and systems. Applying wafer-level and chip-scale approaches new designs will allow for hermetic encapsulation of sensitive structures, as well as simple, multi-functional electrical, microfluidic, optical and thermal interconnection of system components. This project will demonstrate feasibility of a method to package electronic components in such a way that a) high frequency performance is optimized; b) cost is minimized; c) the integrity of the components are protected both during packaging and over life; d) application flexibility is maintained. The basic process steps will be demonstrated and prototypes developed for wafer-level chip-scale packaging for optical components using proprietary techniques for temporary wafer bonding of pre-thinned wafers; formation of through-substrate vias, along with insulation and metallization of the vias; and joining by solder or other methods. The proposed packaging techniques allow for a variety of devices to be placed in a miniature sealed cavity, having provision for maintenance of vacuum over life. Also in conjunction with inkjet printing methods, a single via design may be adapted to fluidics, optics or thermal dissipation.Wafer-level and chip-scale-packaging offers critical advantages of miniaturization, cost reduction, and performance and reliability enhancements. These are, in fact, the historical and future drivers for most of the semiconductor industry. In addition to mainstream semiconductor applications, the approach offers unique solutions for devices such as inertial grade navigation instruments, where performance and reliability enhancements may be of utmost importance.