VIrtual TEst STructure (VITEST)

虚拟测试结构（VITEST）

• 批准号: 0541297
• 负责人: Wojciech Maly
• 金额: $ 27.5万
• 依托单位: Carnegie-Mellon University
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2006
• 资助国家: 美国
• 起止时间: 2006-08-15 至 2011-07-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=0541297&HistoricalAwards=false
• 关键词: VIrtual; TEst; STructure; VITEST

Prop ID: CCF-0541297 PI: Maly, Wojciech Institution: Carnegie-Mellon University Title: VIrtual TEst STructure (VITEST) AbstractModern Integrated Circuits (ICs) are built of elements so small that some of them may be too small to be fabricated correctly on everyone fabricated device. Art of modern IC manufacturing is in choosing such scale of miniaturization IC elements (typically transistors) that pushes available technology to its limits, i,e, to the stage in which number of fabricated ICs that work correctly is acceptable and at the same time the number of elements in a single IC as large as possible (by making them as small as possible).To achieve such a balance one must understand specific circumstances causing IC malfunction. Typically such knowledge is acquired by using special purpose test structures, which are fabricated instead of normal IC and therefore are wasting very expensive manufacturing capacity. The key idea of the research covered by this project is in the use of IC products themselves for calibration of manufacturing yield models. These models form a foundation of methodologies used for assessment probability of IC malfunctions.

项目ID：CCF-0541297主要研究者：Maly，Wojciech机构：Bermigie-Mellon University标题：虚拟测试结构（VITEST） 现代集成电路（IC）是由非常小的元件组成的，其中一些元件可能太小而不能在每个制造的设备上正确地制造。现代IC制造的技术在于选择这种规模的小型化IC元件（通常是晶体管），其将可用技术推向其极限， 也就是说，到了这样一个阶段，在这个阶段中，可以接受正确工作的集成电路的数量，同时单个集成电路中的元件数量尽可能大（通过使它们尽可能小）。为了实现这种平衡，必须了解导致集成电路故障的特定情况。典型地，通过使用专用测试结构来获得这样的知识，专用测试结构被制造而不是普通IC，因此浪费了非常昂贵的制造能力。本项目研究的核心思想是利用集成电路产品本身来校准制造成品率模型。这些模型构成了用于评估IC故障概率的方法论的基础。