VIrtual TEst STructure (VITEST)
VIrtual TEst STructure (VITEST)
批准号:
0541297
负责人:
Wojciech Maly
金额:
$27.5万
依托单位国家:
美国
项目类别:
Standard Grant
财政年份:
2006
资助国家:
美国
项目状态:
已结题
起止时间:
2006-08-15 至 2011-07-31
中文摘要
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英文摘要
Prop ID: CCF-0541297 PI: Maly, Wojciech Institution: Carnegie-Mellon University Title: VIrtual TEst STructure (VITEST) AbstractModern Integrated Circuits (ICs) are built of elements so small that some of them may be too small to be fabricated correctly on everyone fabricated device. Art of modern IC manufacturing is in choosing such scale of miniaturization IC elements (typically transistors) that pushes available technology to its limits, i,e, to the stage in which number of fabricated ICs that work correctly is acceptable and at the same time the number of elements in a single IC as large as possible (by making them as small as possible).To achieve such a balance one must understand specific circumstances causing IC malfunction. Typically such knowledge is acquired by using special purpose test structures, which are fabricated instead of normal IC and therefore are wasting very expensive manufacturing capacity. The key idea of the research covered by this project is in the use of IC products themselves for calibration of manufacturing yield models. These models form a foundation of methodologies used for assessment probability of IC malfunctions.
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Collaborative Research: SGER: Layout Generation Tools for Double-Gate-Transistor-Array-Based IC Designs
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批准号:0904122
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项目类别:Standard Grant
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资助金额:$3.27万
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财政年份:2009
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负责人:Wojciech Maly
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依托单位:
Easily Manufacturable Implementation of Large Area Defect Tolerant IC's
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批准号:8822805
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项目类别:Standard Grant
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资助金额:$31.51万
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财政年份:1989
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负责人:Wojciech Maly
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依托单位:
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