Collaborative Research: SGER: Layout Generation Tools for Double-Gate-Transistor-Array-Based IC Designs

合作研究：SGER：基于双栅极晶体管阵列的 IC 设计的布局生成工具

• 批准号: 0904122
• 负责人: Wojciech Maly
• 金额: $ 3.27万
• 依托单位: Carnegie-Mellon University
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2009
• 资助国家: 美国
• 起止时间: 2009-07-01 至 2011-06-30
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=0904122&HistoricalAwards=false
• 关键词: Collaborative; Research; SGER; Layout; Generation

Title: Collaborative Research: SGER: Layout Generation Tools for Double-Gate-Transistor-Array-Based IC DesignsCCF - 0904122 Maly, Wojciech (Carnegie-Mellon University)CCF - 0904124 Marek-Sadowska, Malgorzata (University of California-Santa Barbara)ABSTRACTThe proposed project aims to demonstrate the feasibility of an approach that can potentially remedy the huge productivity crisis plaguing the IC industry. The PIs propose a design methodology utilizing transistor-array-based canvases. The building block of a canvas is a vertical slit (VeS), dual-gate, junction-less transistor that can be fabricated with an SOI-like process. Canvases can be configured into useful circuits by customizing interconnects fabricated in a metallization process. In this way, one of the show stoppers of the modern design, lithographic imperfections, can be almost completely eliminated. The research proposed here is focused on developing basic layout tools for VeS-transistor arrays to show that dense transistor layouts are feasible, and to quantify the performance and power consumption of circuits built from VeS transistors.If successful, the methodology may have a huge effect on IC manufacturing and design practices.The design and manufacturing strategy proposed here has a very real chance of helping designersto make rapid use of the huge number of transistors available on a single chip without sacrificing performance and cost. The VeS transistor arrays can also serve as foundations for 3-D integration.

标题：合作研究：SGER：用于基于双栅极晶体管阵列的IC设计的布局生成工具CCF- 0904122 Maly，Wojciech （梅伦大学）CCF - 0904124 Marek-Sadowska，Malgorzata（加州大学圣巴巴拉分校）摘要拟议的项目旨在证明一种方法的可行性，这种方法可以潜在地补救困扰IC行业的巨大生产力危机。PI提出了一种利用基于晶体管阵列的画布的设计方法。画布的构建块是一个垂直狭缝（VeS），双栅极，无结晶体管，可以用SOI类工艺制造。通过定制在金属化工艺中制造的互连，可以将画布配置成有用的电路。通过这种方式，现代设计中的显示障碍之一，平版印刷缺陷，几乎可以完全消除。这里提出的研究重点是开发VeS晶体管阵列的基本布局工具，以表明密集晶体管布局是可行的，并量化由VeS晶体管构建的电路的性能和功耗。如果成功，该方法可能对IC制造和设计实践产生巨大的影响。这里提出的设计和制造策略有一个非常真实的机会，可以帮助设计人员快速利用在单个芯片上提供大量晶体管，而不牺牲性能和成本。VeS晶体管阵列还可以作为3D集成的基础。