Collaborative Research: SGER: Layout Generation Tools for Double-Gate-Transistor-Array-Based IC Designs

题目：合作研究：SGER：基于双栅极晶体管阵列的IC设计的布局生成工具sccf - 0904122 Maly， Wojciech（卡内基-梅隆大学）CCF - 0904122 Marek-Sadowska, Malgorzata（加州大学圣巴巴拉分校）摘要提出的项目旨在证明一种方法的可行性，这种方法可以潜在地解决困扰IC行业的巨大生产力危机。pi提出了一种利用基于晶体管阵列的画布的设计方法。画布的构建块是一个垂直狭缝（VeS），双栅极，无结晶体管，可以用类似于soi的工艺制造。画布可以配置成有用的电路，通过定制互连在金属化过程中制造。这样一来，现代设计的阻碍因素之一——平版印刷缺陷——就可以几乎完全消除。本文提出的研究重点是开发VeS晶体管阵列的基本布局工具，以证明密集晶体管布局是可行的，并量化由VeS晶体管构建的电路的性能和功耗。如果成功，该方法可能对集成电路制造和设计实践产生巨大影响。这里提出的设计和制造策略非常有可能帮助设计人员在不牺牲性能和成本的情况下快速使用单个芯片上可用的大量晶体管。VeS晶体管阵列也可以作为3d集成的基础。

Title: Collaborative Research: SGER: Layout Generation Tools for Double-Gate-Transistor-Array-Based IC DesignsCCF - 0904122 Maly, Wojciech (Carnegie-Mellon University)CCF - 0904124 Marek-Sadowska, Malgorzata (University of California-Santa Barbara)ABSTRACTThe proposed project aims to demonstrate the feasibility of an approach that can potentially remedy the huge productivity crisis plaguing the IC industry. The PIs propose a design methodology utilizing transistor-array-based canvases. The building block of a canvas is a vertical slit (VeS), dual-gate, junction-less transistor that can be fabricated with an SOI-like process. Canvases can be configured into useful circuits by customizing interconnects fabricated in a metallization process. In this way, one of the show stoppers of the modern design, lithographic imperfections, can be almost completely eliminated. The research proposed here is focused on developing basic layout tools for VeS-transistor arrays to show that dense transistor layouts are feasible, and to quantify the performance and power consumption of circuits built from VeS transistors.If successful, the methodology may have a huge effect on IC manufacturing and design practices.The design and manufacturing strategy proposed here has a very real chance of helping designersto make rapid use of the huge number of transistors available on a single chip without sacrificing performance and cost. The VeS transistor arrays can also serve as foundations for 3-D integration.