Easily Manufacturable Implementation of Large Area Defect Tolerant IC's

该项目正在开发在标准IC生产线上制造大面积集成电路(IC)的技术。正在考虑的电路是当前电路面积的10到50倍。研究人员正在对集成电路的制造缺陷进行表征，并对其进行分析以预测芯片良率。根据这些预测，他们可以在各种技术中进行选择，以实现缺陷容限的片上重新配置。

This project is developing techniques for fabricating large-area integrated circuits (IC) on standard IC fabrication lines. The circuits under consideration are 10 to 50 times the area of current circuits. The researchers are characterizing manufacturing defects on integrated circuits, and analyzing these to predict chip yields. From these predictions they can select among various techniques for on-chip reconfiguration for defect tolerance.