Self-Adjusting Architectures/Circuits for Improved Performance and Reduced Design Complexity

纳米级集成电路的最新趋势不会因当代架构创新而得到缓解，并将在未来微处理器的设计中引入重大瓶颈。首先，高性能电路的模型越来越复杂，这使得很难确定可以帮助架构师优化设计的关键特性。其次，工艺参数和环境变量（如电源和温度）的可变性都在增加。这些不断增加的变化直接反映在微处理器产量统计数据中，因为越来越多的制造芯片无法达到性能目标。此外，不直接考虑电路级原因的架构修改将很难（如果不是不可能的话）从这些损失中恢复。在没有干预的情况下，未来处理器的设计周期将被与模型复杂性和参数变化相关的详尽验证所主导。该项目提供了一种范式转换，其中设计周期的特点是集中分析可能的故障，并增加了自我监控、自我调整机制，这些机制既可以提高产量，增加性能，又可以减少验证的需求。这种方法的核心在于能够容忍变化的灵活架构的设计。本项目特别涉及：(1)基于物理特性的变化感知架构模型，对处理器中的关键部分和可能的故障进行初步估计至关重要，以及权衡研究；(2)考虑电路物理方面的创新自调整架构，可以根据现场读数重新配置；(3)在芯片上放置传感和监测元件的算法，以及自适应结构的部署和所需自适应类型的确定；(4)电路合成算法，确定如何调整处理器以提高产量和性能。该项目直接解决了微处理器行业的一个关键问题：工艺变化，因此将具有显著的商业和社会效益。学术上的好处包括设计自动化、电路和建筑研究人员和教育工作者之间的密切互动。这将为学习开辟新的途径，并提出一系列新的有趣的挑战。

Recent trends of nanoscale integrated circuits will not be mitigated by contemporary architectural innovations and will introduce significant bottlenecks in the design of future microprocessors. First, the growing complexity of models for high performance circuits make it difficult to identify critical characteristics which could aid architects in optimizing the design. Second, there is an increasing variability both in the process parameters and in environmental variables such as power supply and temperature. These increasing variations are directly reflected in microprocessor yield statistics as more manufactured chips fail to meet performance targets. Furthermore, it will be difficult if not impossible to recover from these losses with architectural modifications, which do not directly consider the circuit level causes. Without intervention, the design cycle of future processors will be dominated by exhaustive verification related to model complexity and parameter variation. This project offers a paradigm shift where the design cycle features focused analysis of possible failures and the addition of self-monitoring, self-adjusting mechanisms that can both improve the yield, increase the performance, and reduce the requirements of verification. At the heart of this approach lies the design of flexible architectures that can tolerate variations. Particularly, this project involves generation of: (1) variation-aware architectural models which are based on physical properties and are essential for an initial estimate of the critical segments in the processor and possible failures, as well as tradeoff studies, (2) innovative self-adjusting architectures which consider physical aspects of circuits and can be reconfigured based on in-field readings, (3) algorithms for placement of sensing and monitoring elements on the chip as well as the deployment of the adaptive structures and determination of the adaptation type needed, and (4) circuit synthesis algorithms, which determine how to adjust processors for improved yield and performance. This project directly attacks a critical problem in the microprocessor industry: process variation, and hence would have significant commercial and social benefits. Academic benefits include the close interaction between the design automation, circuits, and architecture researchers and educators. This will open new avenues for learning and present a new set of interesting challenges.