CAREER: Parallel, Scalable, and Efficient I/O for Network Servers

职业：网络服务器的并行、可扩展且高效的 I/O

• 批准号: 0546140
• 负责人: Scott Rixner
• 金额: $ 40万
• 依托单位: William Marsh Rice University
• 依托单位国家: 美国
• 项目类别: Continuing Grant
• 财政年份: 2006
• 资助国家: 美国
• 起止时间: 2006-04-01 至 2012-03-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=0546140&HistoricalAwards=false
• 关键词: CAREER; Parallel; Scalable; Efficient; Network

Networking has become an integral part of modern computer systems, so the architecture of the network subsystem is a critical design consideration. In the past, the performance of the network subsystem has kept up with network bandwidth growth because of the exponential rate of improvement in processor performance. However, to counteract the increasing complexity and wire-limited nature of modern uniprocessors, chip multiprocessing and simultaneous multithreading have emerged as dominant microprocessor architectures. These architectures sacrifice uniprocessor performance growth in favor of increased parallelism, so current network subsystems that rely on single-thread performance will be unable to saturate the network in future systems. This project will develop new network subsystem architectures to efficiently utilize next generation microprocessors and maximize network performance. This research will improve networking parallelism and scalability by considering all levels of the network subsystem, including the operating system's network stack, network device drivers, the I/O system, and network interface hardware. This will result in a restructuring of the hardware and software interfaces within the network subsystem to provide mechanisms for parallel communication and collaborative processing between microprocessors and network interfaces. This project will also be used to expose students to system-level networking issues in both undergraduate and graduate computer systems and architecture courses.

网络已成为现代计算机系统的一个组成部分，因此网络子系统的体系结构是一个关键的设计考虑因素。在过去，由于处理器性能的指数增长率，网络子系统的性能一直与网络带宽的增长保持同步。然而，为了对抗现代单处理器的日益增加的复杂性和线受限的性质，芯片多处理和同时多线程已经成为主导的微处理器架构。这些体系结构牺牲了单处理器性能的增长，而有利于提高并行性，因此目前依赖于单线程性能的网络子系统将无法在未来的系统中使网络饱和。该项目将开发新的网络子系统架构，以有效地利用下一代微处理器并最大限度地提高网络性能。这项研究将提高网络并行性和可扩展性，考虑所有级别的网络子系统，包括操作系统的网络堆栈，网络设备驱动程序，I/O系统，和网络接口硬件。这将导致网络子系统内的硬件和软件接口的重组，以提供微处理器和网络接口之间的并行通信和协作处理的机制。这个项目也将用于让学生在本科和研究生计算机系统和架构课程中接触系统级网络问题。