CSR: Small: Breaking the Address Translation Barrier in Large Memory Systems

今天，基于商品的廉价计算机系统，现成的组件可以支持数百GB的内存。传统上，对大内存系统的需求主要来自数据库操作员，用于大容量事务处理等应用程序。 然而，如今，从使用虚拟化的服务器整合到Web 2.0应用程序的基础设施，各种各样的应用程序推动了对这种大内存系统的需求。在100 GB或更大的规模下，对于许多这些应用程序，虚拟内存访问成为瓶颈。 具体而言，地址转换的开销急剧增加。 大页面可以通过显著增加转换后备缓冲区（TLB）覆盖率来缓解此问题。 然而，这些应用经常表现出较差的时间和/或空间参考局部性。 因此，即使是大页面，TLB的命中率是非常低的。本研究将开发新的架构机制和操作系统的支持，以减轻地址转换的成本。解决这个问题的有效方法包括在专用硬件中缓存页表的内部级别，提供硬件支持以利用操作系统中物理上连续的内存预留，以及重新检查页表组织以获得大地址空间。 本研究将探索所有这些技术，并仔细考虑操作系统中的内存分配和管理与硬件中的地址转换开销之间的相互作用。本研究将改变在未来系统上执行地址转换的方式，使数百GB的内存得到有效利用。 目前，大型内存机器遭受地址转换瓶颈，限制了整体性能。 由于这些机器消耗大量电力，这导致电力效率低下，浪费能源和金钱。 更有效的地址转换将带来显著的改进，特别是在拥有大量大内存机器的数据中心。

Today, inexpensive computer systems based on commodity, off-the-shelf components can support hundreds of gigabytes of memory. Traditionally, the demand for large-memory systems came predominantly from the operators of databases for applications such as high-volume transaction processing. Today, however, a much wider variety of applications drive the demand for such large-memory systems, ranging from server consolidation using virtualization to infrastructure for Web 2.0 applications. At a scale of 100GB or more, for many of these applications, virtual memory access becomes a bottleneck. Specifically, the overhead of address translation increases dramatically. Large pages can mitigate this problem by significantly increasing translation look-aside buffer (TLB) coverage. However, all too often these applications exhibit poor temporal and/or spatial locality of reference. Thus, even with large pages, the TLB hit rate is very low.This research will develop novel architectural mechanisms and operating systems support to mitigate the cost of address translation. Effective approaches to this problem include caching internal levels of the page table in dedicated hardware, providing hardware support to exploit physically contiguous memory reservations within the operating system, and re-examining page table organizations for large address spaces. This research will explore all of these techniques and carefully consider the interactions between memory allocation and management in the operating system and address translation overhead in the hardware.This research will transform the way in which address translation is performed on future systems, enabling the effective use of hundreds of gigabytes of memory. Currently, large memory machines suffer from address translation bottlenecks, limiting overall performance. As these machines consume significant amounts of power, this leads to poor power efficiency, wasting both energy and money. More efficient address translation will lead to significant improvements, especially in datacenters with numerous large memory machines.