CAREER: System-level Design of Network-on-Chip Architectures
职业:片上网络架构的系统级设计
基本信息
- 批准号:0546462
- 负责人:
- 金额:$ 40万
- 依托单位:
- 依托单位国家:美国
- 项目类别:Continuing Grant
- 财政年份:2006
- 资助国家:美国
- 起止时间:2006-03-15 至 2013-02-28
- 项目状态:已结题
- 来源:
- 关键词:
项目摘要
0546462PI: Karamvir S. ChathaArizona State UniversityCAREER: System-level Design of Network-on-Chip ArchitecturesSystem-on-Chip (SoC) architectures in future will be implemented in less than 50nm technology and include tens to hundreds of heterogeneous processing element blocks operating in the multi-GHz range. The on-chip interconnection network will be a key factor in determining the performance and power consumption of these multi-core devices. Packet switched interconnection networks or Network-on-Chip (NoC) has emerged as an attractive alternative to traditional bus-based architectures for satisfying the communication requirements of these multi-core SoC architectures. The key challenge in NoC design is to produce a complex, high performance and low energy architecture under tight time to market requirements. The NoC architectures would support the communication demands of hundreds of cores under stringent performance constraints. In addition to the complexity, the NoC designers would also have to contend with the physical challenges of design in nanoscale technologies. The NoC design problem would entail a joint optimization of the thermal profile of the system-level floorplan and power consumption of the network. All these factors coupled with the requirement for short turn around times raises the need for an intellectual property (IP) re-use methodology that is well supported with design and optimization techniques, and performance evaluation models.The project accomplishes the following three tasks for the IP re-use based methodology for design of NoC architectures: (i) Development of design and optimization techniques for NoC architectures: The techniques support design of NoC architectures with both regular and custom topologies. The design techniques address the issue of thermal floorplanning, high power consumption, and long signal propagation delays that arise in nanoscale technologies. (ii) Development of a customizable IP block for NoC router: The customizable features of the router architecture permit its integration into NoC design flows for both regular and application-specific topologies with multiple levels of quality-of-service. (iii) Development of performance and power consumption models for the customizable router: The models that are at various levels of abstraction enable design space exploration, optimization and performance verification of NoC architectures. The education contributions of the project include development of catalogue of course projects on NoC, recruitment of undergraduate students for graduate school, technology transfer through industry focused curriculum, and increased participation of under-represented groups. Intellectual merit: Multi-core SoC devices are the only solution to the power consumption roadblocks of technology scaling. The project overcomes a key challenge to the successful realization of multi-core SoC devices in deep nanoscale technologies. The project also achieves an appreciable increase in design productivity by enabling the migration of VLSI design to the next higher level of abstraction, namely the system level. Broad impact: SoC architectures that are enabled by the project are the essential component of embedded devices which have permeated through all facets of human activities. Therefore, the project significantly benefits every interface of human-computer interaction including medical instruments, cell phones, automobile controllers, entertainment units, assistive devices and so on. Education impact includes integration of system-level design courses into the undergraduate and graduate curriculum.
0546462 PI:Karamvir S. Chatha Arizona State University亚利桑那州立大学片上网络体系结构的系统级设计未来的片上系统(SoC)体系结构将以小于50 nm的技术实现,并包括数十到数百个在多GHz范围内工作的异构处理单元块。片上互连网络将是决定这些多核器件性能和功耗的关键因素。分组交换互连网络或片上网络(NoC)已经成为传统的基于总线的架构的有吸引力的替代方案,以满足这些多核SoC架构的通信要求。片上网络设计中的关键挑战是在严格的上市时间要求下产生复杂、高性能和低能耗的架构。NoC架构将在严格的性能约束下支持数百个核的通信需求。除了复杂性之外,NoC设计者还必须应对纳米级技术设计的物理挑战。NoC设计问题将需要对系统级布图规划的热分布和网络的功耗进行联合优化。所有这些因素再加上对短周转时间的要求,提出了对知识产权(IP)重用方法的需求,该方法具有良好的设计和优化技术以及性能评估模型的支持。该项目完成了以下三项任务,即基于IP重用的NoC架构设计方法:(i)开发NoC架构的设计和优化技术:这些技术支持具有常规拓扑和定制拓扑的NoC架构的设计。该设计技术解决了纳米级技术中出现的热布局规划、高功耗和长信号传播延迟的问题。(ii)为NoC路由器开发可定制的IP块:路由器架构的可定制功能允许其集成到具有多个服务质量级别的常规和特定应用拓扑的NoC设计流程中。(iii)为可定制的路由器开发性能和功耗模型:处于各种抽象级别的模型可以实现NoC架构的设计空间探索,优化和性能验证。该项目对教育的贡献包括:编制NoC课程项目目录、为研究生院招收本科生、通过以行业为重点的课程进行技术转让,以及增加代表性不足群体的参与。智力优势:多核SoC设备是解决技术扩展功耗障碍的唯一解决方案。该项目克服了在深纳米级技术中成功实现多核SoC器件的关键挑战。该项目还实现了设计生产力的显着提高,使超大规模集成电路设计的迁移到下一个更高的抽象层次,即系统级。广泛影响:该项目支持的SoC架构是嵌入式设备的重要组成部分,已经渗透到人类活动的各个方面。因此,该项目对包括医疗仪器、手机、汽车控制器、娱乐设备、辅助设备等在内的人机交互的每一个接口都有显著的好处。教育影响包括将系统级设计课程整合到本科和研究生课程中。
项目成果
期刊论文数量(0)
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Karamvir Chatha其他文献
Karamvir Chatha的其他文献
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{{ truncateString('Karamvir Chatha', 18)}}的其他基金
System-level Design of Streaming Applications on Domain Specific Multi-core Processors
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- 批准号:
0551678 - 财政年份:2006
- 资助金额:
$ 40万 - 项目类别:
Standard Grant
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