SGER: Fast and Scalable Simulation for Multicore and Multithreaded Processor by Using Commodity FPGA Boards

我们提出了一个探索性项目，利用商用FPGA板集群构建一个快速、可扩展的架构仿真平台。它本质上是并行的：一块FPGA板模拟一个处理器核心，一组FPGA板模拟一个多核处理器芯片，一组这样的组模拟一个完整的计算集群。通过使用赛灵思FPGA板的性能数据进行仔细分析，我们表明减速将小于两个数量级，这使得全面评估是可行的。相比之下，软件模拟器的速度减慢至少是五个数量级。系统是可扩展的，因为可以通过添加更多的FPGA板来增加系统大小。该平台价格合理，灵活，易于复制，可以被行业和学术研究人员广泛使用。高性能计算应用对我们的日常生活有着深远的影响，其计算需求永远无法得到充分满足。然而，如果没有一个快速的仿真平台，多核和多线程处理器在制造出来之前是无法被大规模并行程序评估的。拟议的研究消除了这一限制。它将促使人们尽早考虑和评估提高处理器效率的系统级方法，为计算机架构师提供重要的输入。因此，它可以帮助减少试验和错误，这将是非常昂贵的，并将延迟高性能计算系统的改进。提出的实验支持将使计算机体系结构和高性能计算社区的其他研究人员受益，并帮助他们在真正的机器可用之前看到彼此的需求。

Intellectual MeritWe propose an exploratory project to build a fast and scalable architectural simulationplatform using clusters of commodity FPGA boards. It is inherently parallel: A FPGA board simulates aprocessor core, a group of FPGA boards simulates a multicore processor chip, and a cluster of such groupssimulates a full computing cluster. By careful analysis using the performance data of Xilinx FPGA board,we show that the slowdown will be less than two orders of magnitude, which makes full-scale evaluationfeasible.By comparison, the slowdown of a software simulator will be at least five orders of magnitude. Thesystem is scalable in that one can increase the system size by adding more FPGA boards. The platform isalso affordable, flexible, and easy to replicate, and can be widely used by industry and academic researchers.Boarder ImpactHigh Performance computing applications have deep impact in our daily life and their computing demand would never be fully satisfied. However, without a fast simulation platform, multicore and multithreaded processors are not being evaluated by large-scale parallel programs until they have been manufactured. The proposed research removes this limit. It will prompt early consideration and evaluation of system-level methods for improving processor efficiency, providing important input to computer architects.Thus, it may help reduce the trials and errors that would be very expensive and would delay theimprovement of high performance computing systems. The proposed experiment support will benefit otherresearchers in both computer architecture and high-performance computing communities, and help them seethe needs of each other before the real machines are available.