CSR---EHS: Scheduling Techniques for Reconfigurable Embedded Computing

对提高性能的持续追求和降低功耗的矛盾需求对嵌入式计算的发展提出了严峻的挑战。可重构计算通过为基于硬件的执行提供灵活的媒介来解决这些问题。应用程序代码的计算密集型部分在可重构硬件（如现场可编程门阵列（fpga））中实现，以加速应用程序，降低其功耗要求，或两者兼而有之。传统的微处理器执行未在硬件中实现的应用程序部分，提供混合的软件/硬件执行模型。然而，与传统的自定义硬件不同，可重构硬件的实际功能在执行期间是可变的，以便在应用程序内部和跨应用程序实现不同的硬件功能。因此，硬件实现的性能和功耗优势与解决随时间变化的计算需求的灵活性相辅相成，这种时间跨度可以用天、秒甚至微秒来衡量。因此，可重构计算是未来嵌入式计算的一种强大而引人注目的计算范式。该项目解决了在主流嵌入式设备中使用可重构计算的主要障碍之一：缺乏适合现代多任务多线程嵌入式系统的系统软件支持。在这项研究中，该项目正在开发操作系统级技术，以便在多个执行线程和进程之间调度和分配可重构硬件，以实现最佳的总体系统级性能和节能。正在研究的调度主题包括：计算密集型功能与硬件或软件的动态绑定，针对不同区域/性能/功率权衡的不同硬件实现之间的选择，基于变化的系统负载的自适应调度，以及硬件功能的预测性预取。有了强大的运行时调度算法，未来的嵌入式设备将获得可重构计算的全部潜力。

The persistent drive for increased performance and the contradictory need to reduce power consumption pose serious challenges to the advancement of embedded computing. Reconfigurable computing answers these by providing a flexible medium for hardware-based execution. Compute-intensive sections of application code are implemented in reconfigurable hardware, such as field-programmable gate arrays (FPGAs), to accelerate the application, reduce its power requirements, or both. A traditional microprocessor executes application parts not implemented in hardware, providing a mixed software/hardware execution model. However, unlike traditional custom hardware, the actual functionality of reconfigurable hardware is changeable during execution to implement different hardware functions within and across applications. The performance and power benefits of hardware implementation are therefore complemented by the flexibility to address computing needs that change over time, where that time-span may be measured in days, seconds, or even microseconds. Reconfigurable computing is therefore a powerful and compelling computing paradigm for future embedded computing. This project addresses one of the key barriers to the use of reconfigurable computing in mainstream embedded devices: the lack of systems software support appropriate to modern multi-tasking multi-threaded embedded systems. In this research, the project is developing OS-level techniques to schedule and allocate reconfigurable hardware between multiple executing threads and processes in order to achieve the best overall system-level performance and power-savings. Scheduling topics under investigation include: dynamic binding of compute-intensive functions to hardware or software, choosing between different hardware implementations targeting different area/performance/power tradeoffs, adaptive scheduling based on changing system loads, and predictive pre-fetching of hardware functions. With powerful run-time scheduling algorithms, embedded devices of the future will reap the full potential of reconfigurable computing.