Reconfigurable Computing Memory System Integration

可重构计算内存系统集成

• 批准号: 0702605
• 负责人: Katherine Morrow
• 金额: $ 30万
• 依托单位: University of Wisconsin-Madison
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2007
• 资助国家: 美国
• 起止时间: 2007-09-01 至 2011-08-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=0702605&HistoricalAwards=false
• 关键词: Reconfigurable; Computing; Memory; System; Integration

The persistent drive for increased performance and more functionality poses continuing challenges to computing. Reconfigurable computing is an alternative method to address these concerns: complex operations execute as hardware circuits made from reconfigurable logic instead of as slower sequential instructions on a programmable processor. This research examines the integration of reconfigurable logic into modern computing systems consisting of multiple processor cores, multiple levels of memory hierarchy, and virtual memory support. The project compares different cache-based and queue-based memory structures for use in novel memory interfaces that connect reconfigurable logic to system memory at various connection points within the memory hierarchy. New specialized memory controller designs optimized for reconfigurable logic and flexible enough for different application types will allocate these memory structures to the data needed by the reconfigurable logic. The memory controller designs will also support virtual memory to ensure memory protection, a necessary feature for today's computing systems. The research will evaluate these different memory interfaces and controllers to identify those best suited for reconfigurable computing, supporting the needed types of memory accesses, and providing the memory bandwidth performance required by circuits implemented in reconfigurable logic. The overall goal of the project is to elevate reconfigurable computing to a mainstream technique for complex computing systems, providing power savings and performance benefits to a wide variety of applications.

对提高性能和更多功能的持续驱动给计算带来了持续的挑战。可重构计算是解决这些问题的另一种方法：复杂的操作作为由可重构逻辑组成的硬件电路执行，而不是作为可编程处理器上较慢的顺序指令执行。这项研究考察了可重构逻辑与现代计算系统的集成，该系统由多个处理器核心、多层内存层次结构和虚拟内存支持组成。该项目比较了不同的基于高速缓存和基于队列的存储器结构，用于将可重新配置的逻辑连接到存储器层次结构内不同连接点的系统存储器的新型存储器接口中。针对可重构逻辑进行了优化并且足够灵活地用于不同应用类型的新的专用存储器控制器设计将这些存储器结构分配给可重构逻辑所需的数据。内存控制器设计还将支持虚拟内存，以确保内存保护，这是当今计算系统的必要功能。研究将评估这些不同的存储器接口和控制器，以确定最适合可重构计算的接口和控制器，支持所需类型的存储器访问，并提供可重构逻辑中实现的电路所需的存储器带宽性能。该项目的总体目标是将可重构计算提升为复杂计算系统的主流技术，为各种应用程序提供节能和性能优势。