MRI: Acquisition of Computing Resources for Management of Reliability through Data Classification and Voltage Overscaling

该项目设计、实现和模拟体系结构组件，以计算其功率需求，并开发详细的容错模型，旨在为任务（高性能刀片、硬盘驱动器、千兆以太网、软件）获得适当的基础设施。提出了嵌入式系统和微架构设计的转变，工作重点是设计利用应用容忍度降低精度的嵌入式系统。容忍度通常用于适应通信和网络性能中服务质量的变化。在提出一组静态和动态机制来跟踪涉及控制的计算的同时，该项目将这种容忍度推进到嵌入式处理器的微架构中。该项目通过评估将计算和数据映射到具有不同级别软错误保护的架构组件和降低精度的组件（通过电压过缩放和/或功率门控节省功率）的潜力，检查了两种类型的错误，这两种类型的错误受益于跟踪数据类别。建议使用一种通用的编译器和体系结构机制，可以在任何代码上运行，但设计用于利用可以以某种形式的输出保真度换取宽松精度要求的应用程序。

This project, designing, implementing, and simulating architectural components to calculate their power requirements and developing detailed models of fault-tolerance, aims at acquiring appropriate infrastructure for the tasks (high-performance Blades, hard drive, Gigabit Ethernet, software). Proposing a shift in the design of embedded systems and microarchitectures, the work focuses on designing embedded systems that exploit application tolerance to reduced accuracy. Tolerance is often used to accommodate variations in quality of service in communication and network performance. While proposing a set of static and dynamic mechanisms to track computations involving control, the project pushes this tolerance into microarchitecture of embedded processors. The project examines two types of errors that benefit from tracking the data categories by evaluating the potential of mapping computations and data to -Architectural components with differing levels of soft error protection and-Reduced precision components, that save power through voltage overscaling and/or power gating. Proposed are a general compiler and architecture mechanisms that will function on any code, but are designed to exploit applications that can trade some form of output fidelity for relaxed accuracy requirements.