MRI: Acquisition of Computing Resources for Management of Reliability through Data Classification and Voltage Overscaling

该项目设计、实施和模拟架构组件，以计算其功耗需求，并开发详细的容错模型，旨在为任务（高性能刀片式服务器、硬盘驱动器、千兆以太网、软件）获取适当的基础设施。提出了嵌入式系统和微架构设计的转变，工作重点是设计嵌入式系统，利用应用程序的公差，以降低精度。容差通常用于适应通信和网络性能中服务质量的变化。在提出一组静态和动态机制来跟踪涉及控制的计算的同时，该项目将这种容差推到嵌入式处理器的微架构中。 该项目通过评估将计算和数据映射到具有不同级别的软错误保护的架构组件和通过电压过调节和/或功率门控节省功率的降低精度组件的潜力，来检查两种类型的错误，这些错误从跟踪数据类别中受益。提出了一个通用的编译器和架构机制，将在任何代码上运行，但旨在利用应用程序，可以贸易某种形式的输出保真度放松精度要求。

This project, designing, implementing, and simulating architectural components to calculate their power requirements and developing detailed models of fault-tolerance, aims at acquiring appropriate infrastructure for the tasks (high-performance Blades, hard drive, Gigabit Ethernet, software). Proposing a shift in the design of embedded systems and microarchitectures, the work focuses on designing embedded systems that exploit application tolerance to reduced accuracy. Tolerance is often used to accommodate variations in quality of service in communication and network performance. While proposing a set of static and dynamic mechanisms to track computations involving control, the project pushes this tolerance into microarchitecture of embedded processors. The project examines two types of errors that benefit from tracking the data categories by evaluating the potential of mapping computations and data to -Architectural components with differing levels of soft error protection and-Reduced precision components, that save power through voltage overscaling and/or power gating. Proposed are a general compiler and architecture mechanisms that will function on any code, but are designed to exploit applications that can trade some form of output fidelity for relaxed accuracy requirements.