NSF CCF-CPA: Reliability in the Face of Variability under Nanoscale Technology Scaling

在过去的几十年里，技术规模使集成电路(IC)行业实现了巨大的增长。虽然摩尔定律似乎很有力，但当前和未来纳米级技术(例如，45 nm及以下)中的细微线宽存在几个障碍，可能会限制器件的持续缩放，限制频率改进，并导致未来微处理器的泄漏功率增加。更糟糕的是，电压和温度波动是由不断增加的功率消耗和试图降低功率的技术引起的。这些变化的综合影响迫使设计者纳入更大的设计余量，以确保可靠的运行。这项建议寻求以合作的方式在电路和体系结构层面上解决可变性问题，以确保下一代计算系统的可靠运行。第一个重点是研究电路和架构解决方案，以应对对片上存储器可靠性的日益关注，并为每个制造的芯片获得一致的性能水平。这些担忧源于在大规模技术中制造晶体管时的变化。第二个推力旨在通过灵活的电路和架构配置来最大限度地减少芯片关键部件的前述裕度，这些配置可以适应各种变化。第三个推力利用前两个努力来了解可变性的影响，并为容忍可变性的芯片-多处理器设计提供指导方针。

Technology scaling has enabled tremendous growth in the integrated circuits (IC) industry over the past few decades. While Moore's Law seems to be going strong, fine line widths in current and future nanoscale technologies (e.g., 45nm and below) present several obstacles that have the potential to limit continued device scaling, curtail frequency improvements, and cause increased leakage power in future microprocessors. To make matters worse, voltage and temperature fluctuations arise from increasing power dissipation and techniques that attempt to reduce power. The combined impact of these variations forces designers to incorporate larger amounts of design margins in order to guarantee reliable operation. This proposal seeks to address the issue of variability in a cooperative fashion at both the circuit and architecture levels to ensure reliable operation of next-generation computing systems.This proposal outlines work along three main research thrusts. The first thrust investigates circuit and architectural solutions to deal with the growing concern over reliability of on-chip memories and obtaining consistent levels of performance for each manufactured chip. These concerns arise from variations when manufacturing transistors in aggressively-scaled technologies. The second thrust seeks to minimize the aforementioned margins in critical parts of a chip via flexible circuit and architecture configurations that can accommodate variations. The third thrust leverages the first two efforts to understand the impact of variability and to offer guidelines for variability-tolerant chip-multiprocessor designs.