NSF CCF-CPA: Reliability in the Face of Variability under Nanoscale Technology Scaling

在过去的几十年里，技术规模化使集成电路（IC）行业取得了巨大的增长。虽然摩尔定律似乎越来越强大，但当前和未来纳米技术（例如45纳米及以下）的细线宽度存在几个障碍，这些障碍可能会限制设备的持续缩放，限制频率的改进，并导致未来微处理器的泄漏功率增加。更糟糕的是，电压和温度的波动是由不断增加的功耗和试图降低功耗的技术引起的。这些变化的综合影响迫使设计人员纳入更大的设计余量，以保证可靠的运行。本提案旨在以合作方式解决电路和架构级别的可变性问题，以确保下一代计算系统的可靠运行。该提案概述了三个主要研究重点的工作。第一个重点是研究电路和架构解决方案，以处理对片上存储器可靠性的日益关注，并为每个制造芯片获得一致的性能水平。这些担忧来自于大规模生产晶体管时的变化。第二个目标是通过灵活的电路和架构配置来减少芯片关键部分的上述余量，以适应变化。第三个重点是利用前两个努力来理解可变性的影响，并为可容忍可变性的芯片多处理器设计提供指导方针。

Technology scaling has enabled tremendous growth in the integrated circuits (IC) industry over the past few decades. While Moore's Law seems to be going strong, fine line widths in current and future nanoscale technologies (e.g., 45nm and below) present several obstacles that have the potential to limit continued device scaling, curtail frequency improvements, and cause increased leakage power in future microprocessors. To make matters worse, voltage and temperature fluctuations arise from increasing power dissipation and techniques that attempt to reduce power. The combined impact of these variations forces designers to incorporate larger amounts of design margins in order to guarantee reliable operation. This proposal seeks to address the issue of variability in a cooperative fashion at both the circuit and architecture levels to ensure reliable operation of next-generation computing systems.This proposal outlines work along three main research thrusts. The first thrust investigates circuit and architectural solutions to deal with the growing concern over reliability of on-chip memories and obtaining consistent levels of performance for each manufactured chip. These concerns arise from variations when manufacturing transistors in aggressively-scaled technologies. The second thrust seeks to minimize the aforementioned margins in critical parts of a chip via flexible circuit and architecture configurations that can accommodate variations. The third thrust leverages the first two efforts to understand the impact of variability and to offer guidelines for variability-tolerant chip-multiprocessor designs.