NSF CCF-CPA: Reliability in the Face of Variability under Nanoscale Technology Scaling

过去几十年来，技术规模化推动了集成电路 (IC) 行业的巨大发展。 虽然摩尔定律似乎越来越强大，但当前和未来纳米级技术（例如 45 纳米及以下）中的细线宽存在一些障碍，有可能限制器件尺寸的持续缩小、限制频率改进并导致未来微处理器的漏电功率增加。 更糟糕的是，电压和温度波动是由功耗增加和试图降低功耗的技术引起的。这些变化的综合影响迫使设计人员考虑更多的设计余量，以保证可靠的运行。 该提案旨在以合作方式解决电路和架构层面的可变性问题，以确保下一代计算系统的可靠运行。该提案概述了三个主要研究方向的工作。第一个重点研究电路和架构解决方案，以解决人们对片上存储器的可靠性日益增长的担忧，并为每个制造的芯片获得一致的性能水平。 这些问题源于采用大规模技术制造晶体管时的变化。第二个推动力旨在通过可适应变化的灵活电路和架构配置来最小化芯片关键部分中的上述裕度。第三个推动力利用前两个努力来了解可变性的影响，并为容忍可变性的芯片多处理器设计提供指导。

Technology scaling has enabled tremendous growth in the integrated circuits (IC) industry over the past few decades. While Moore's Law seems to be going strong, fine line widths in current and future nanoscale technologies (e.g., 45nm and below) present several obstacles that have the potential to limit continued device scaling, curtail frequency improvements, and cause increased leakage power in future microprocessors. To make matters worse, voltage and temperature fluctuations arise from increasing power dissipation and techniques that attempt to reduce power. The combined impact of these variations forces designers to incorporate larger amounts of design margins in order to guarantee reliable operation. This proposal seeks to address the issue of variability in a cooperative fashion at both the circuit and architecture levels to ensure reliable operation of next-generation computing systems.This proposal outlines work along three main research thrusts. The first thrust investigates circuit and architectural solutions to deal with the growing concern over reliability of on-chip memories and obtaining consistent levels of performance for each manufactured chip. These concerns arise from variations when manufacturing transistors in aggressively-scaled technologies. The second thrust seeks to minimize the aforementioned margins in critical parts of a chip via flexible circuit and architecture configurations that can accommodate variations. The third thrust leverages the first two efforts to understand the impact of variability and to offer guidelines for variability-tolerant chip-multiprocessor designs.