NSF CCF-CPA: Reliability in the Face of Variability under Nanoscale Technology Scaling

在过去的几十年中，技术扩展已经使得集成电路（IC）行业实现了巨大的增长。 虽然摩尔定律似乎越来越强，但当前和未来纳米级技术中的精细线宽（例如，45nm及以下）存在几个障碍，这些障碍有可能限制未来微处理器中的持续器件缩放、削减频率改进并导致泄漏功率增加。 更糟糕的是，电压和温度波动会因功耗增加和试图降低功耗的技术而引起。这些变化的综合影响迫使设计人员纳入更大的设计余量，以保证可靠的操作。 这个建议旨在解决的问题，在电路和架构水平的合作方式，以确保下一代计算systems.This建议概述了工作沿着三个主要的研究方向的可靠操作。第一个推力研究电路和架构解决方案，以应对日益增长的关注片上存储器的可靠性，并获得一致的性能水平，为每个制造的芯片。 这些问题是由在侵略性缩放技术中制造晶体管时的变化引起的。第二个目标是通过灵活的电路和架构配置来最大限度地减少芯片关键部分的上述裕度。第三个推力利用前两个努力，了解可变性的影响，并提供可变性容忍芯片多处理器设计的指导方针。

Technology scaling has enabled tremendous growth in the integrated circuits (IC) industry over the past few decades. While Moore's Law seems to be going strong, fine line widths in current and future nanoscale technologies (e.g., 45nm and below) present several obstacles that have the potential to limit continued device scaling, curtail frequency improvements, and cause increased leakage power in future microprocessors. To make matters worse, voltage and temperature fluctuations arise from increasing power dissipation and techniques that attempt to reduce power. The combined impact of these variations forces designers to incorporate larger amounts of design margins in order to guarantee reliable operation. This proposal seeks to address the issue of variability in a cooperative fashion at both the circuit and architecture levels to ensure reliable operation of next-generation computing systems.This proposal outlines work along three main research thrusts. The first thrust investigates circuit and architectural solutions to deal with the growing concern over reliability of on-chip memories and obtaining consistent levels of performance for each manufactured chip. These concerns arise from variations when manufacturing transistors in aggressively-scaled technologies. The second thrust seeks to minimize the aforementioned margins in critical parts of a chip via flexible circuit and architecture configurations that can accommodate variations. The third thrust leverages the first two efforts to understand the impact of variability and to offer guidelines for variability-tolerant chip-multiprocessor designs.