CSR: SMALL: Virtualized Accelerators for Scalable, Composable Architectures

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This project seeks to develop fundamental technologies to enable the next-generation of computing devices that will power future ubiquitous computing devices such as smartphones, self-driving cars, and autonomous robots. The project develops novel tools and techniques at both the hardware and software layers of computer systems. This project will also train new graduate engineers in architecting complex computing systems, modern software and hardware design methodologies, and cutting edge machine learning techniques. All of these skillsets are in broad demand in US industry but have been underrepresented in STEM education.Heterogeneous architectures comprising general purpose processors, graphics processors, and hardware accelerators designed for specific computing tasks have been widely adopted in today's computing systems for both edge and cloud devices. Specialized computing blocks provide tremendous benefits in energy efficiency. However, a major challenge in the design of such systems is the loss of generality and flexibility that has limited their adoption to a small set of application domains that do not often change. Increased flexibility could be unlocked if accelerators were built from smaller dynamically composable blocks, but existing approaches are difficult to program and scale poorly. This project proposes a design flow to generate a templated System-on-Chip (Soc) with a composable accelerator system that can be physically instantiated for a range of computing platforms. Through a virtualization layer, collections of physical hardware blocks are exposed to software as virtual accelerators. To efficiently search the large design space of the SoC, new design space exploration techniques are under investigation.