Collaborative: Circuit and System Architectures for Self-assembled Nanoscale Computers
Collaborative: Circuit and System Architectures for Self-assembled Nanoscale Computers
批准号:
0702434
负责人:
Alvin Lebeck
金额:
$66.55万
依托单位:
依托单位国家:
美国
项目类别:
Standard Grant
财政年份:
2007
资助国家:
美国
项目状态:
已结题
起止时间:
2007-07-15 至 2012-06-30
中文摘要
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英文摘要
Collaborative Proposal ID(s):702434, 0702410PI names: Alvin Lebeck, Sean WashburnInstitutions: Duke University, U of North CarolinaTitle: Circuit and System Architectures for Self-assembled Nano-scale ComputersAbstractThe rapid advances in computing enjoyed over the last two/three decades have depended heavily on the continued decrease of CMOS transistor sizes. Unfortunately, the capacity for CMOS to continue this trend is finite and will be reached in the near future. This is beyond idle speculation and the semiconductor industry has at present identified the replacement of CMOS as an important, but difficult technological challenge. This research project seeks to develop alternatives to conventional computer system design and fabrication that will be fundamentally important as technology moves past the convenient abstractions built during the first 50+ years of computing.Self-assembled nanoscale systems are a potential candidate for replacing silicon CMOS technologies because of the ability to fabricate nanoscale structures in vast numbers without the need for multi-billion dollar facilities. Coupled with the potential to position molecular-scale components in complex networks, self-assembly is becoming a potent disruptive technology with potentially significant influence on the production of future integrated circuits and microprocessors. Specifically, by leveraging the larger-than-silicon industrial base of chemical manufacturing this research has the potential to create a sea change in the cost model for the fabrication of computer systems.New technologies, such as self-assembly, bring new challenges for the creation of computing systems. The research components of this proposal seek to address the following challenges: 1.) designing high-performance, low-power computer architectures that match the fabrication characteristics of future nanotechnologies, 2.) design and test nanoscale circuits with a focus on device parameter variation, defect modeling and test generation, and automated tools for circuit layout, and 3.) fabrication and characterization of "proof-of-principle" novel self-assembled nanoscale devices (RGFET) and circuits.
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