ITR: Nanoarchitecture: Balancing Regularity, Complexity, and Defect Tolerance using DNA for Nanoelectronic Integration

ITR：纳米架构：使用 DNA 平衡规则性、复杂性和缺陷容限以实现纳米电子集成

• 批准号: 0326157
• 负责人: Alvin Lebeck
• 金额: $ 120万
• 依托单位: Duke University
• 依托单位国家: 美国
• 项目类别: Continuing Grant
• 财政年份: 2003
• 资助国家: 美国
• 起止时间: 2003-09-15 至 2007-08-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=0326157&HistoricalAwards=false
• 关键词: ITR; Nanoarchitecture; Balancing; Regularity; Complexity

Miniaturization in electronics by conventional top-down manufacturing is expected to reach its limit during the next one to two decades. Furthermore, the cost of building fabrication facilities for conventional CMOS may become prohibitive. These issues caused theSemiconductor Industry Association to identify as one of its grand challenges the implementation of non-CMOS solutions that could significantly influence production of future integrated circuits and microprocessors. To meet this challenge, this interdisciplinary project takes a vertically integrated approach that uses a bottom-up process to self-assemble well-defined nanoscale building blocks into functional nanoelectronic structures. This project seeks to overcome existing problems in nanoelectronic integration by using DNA self-assemblies to produce patterned nanostructures.The long-term goal is to construct a computing device through DNA self-assembly of nanoelectronic devices. This goal will be achieved through a series of more modest steps, beginning with the experimental demonstration of DNA assembled nanoelectronic components (e.g., fragmented carbon nanotubes) and then DNA assembly of a very small number of these components into a small circuit. To help guide these efforts, this project will simultaneously explore the impact of this new technology on computer architecture. In particular, the PIs seekto develop architectures that strike a balance between 1) the regularity of large-scale DNA self-assembly patterning capabilities, 2) the complexity required for sophisticated system designs and 3)tolerance to the inevitable defects present in nanoscale systems. The trade-offs between these three architectural properties permeate all aspects of this project and provide the framework for closed-loop feedback among the team members.

传统的自上而下的电子制造的小型化预计将在未来一至二十年内达到极限。此外，为常规CMOS建造制造设施的成本可能变得过高。这些问题使得半导体工业协会将非CMOS解决方案的实施确定为其重大挑战之一，这可能会对未来集成电路和微处理器的生产产生重大影响。为了迎接这一挑战，这个跨学科的项目采取了垂直整合的方法，使用自下而上的过程来自组装定义良好的纳米级构建块到功能纳米电子结构。本项目旨在利用DNA自组装技术制造纳米结构图案，以克服纳米电子集成方面存在的问题。长远目标是通过DNA自组装纳米电子器件来构建计算器件。这一目标将通过一系列更温和的步骤来实现，首先是DNA组装纳米电子组件的实验演示（例如，片段化的碳纳米管），然后DNA将极少量的这些组件组装成一个小电路。为了帮助指导这些工作，该项目将同时探索这种新技术对计算机体系结构的影响。特别是，PI寻求开发在1）大规模DNA自组装图案化能力的规律性，2）复杂系统设计所需的复杂性和3）对纳米级系统中不可避免的缺陷的容忍度之间取得平衡的架构。这三个架构属性之间的权衡渗透到这个项目的各个方面，并为团队成员之间的闭环反馈提供了框架。