RUI: Managing Memory Demands of Data Intensive Workloads in Chip Multiprocessors

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Title: RUI: Managing Memory Demands of Data Intensive Workloads in Chip MultiprocessorsPI: Kelly A. Shaw Until recently, most computer chips contained a single processor; systems with multiple processors were created by using multiple computer chips. Changes in the semiconductor industry are now enabling many, even tens, of processors to reside on a single chip. Placing multiple processors on a given chip makes it possible to execute many different tasks, or processes, on that chip simultaneously, potentially speeding up complex computations. However, it also means that all of those executing tasks must compete for and share all of the other resources on the chip. These resources include locations to store the data used by the processes, wires that enable data to be moved to different locations on the chip, and pins that enable data to be moved on or off of the chip. For applications that use large quantities of data, efficient use of these shared resources will be necessary for fast execution on these chips. The importance of these types of data intensive applications cannot be overstated; financial institutions use them to insure compliance with government standards, scientists use them while performing genome sequence research, and businesses use them to learn about individuals in order to develop new products. This project has two goals. First, this work will quantify the demands these data intensive applications place on a chip's shared resources as more processors are placed on each chip. Understanding the resource needs of these applications will enable identification of problems that prevent these applications from executing quickly on these chips and will expose ways to potentially address these problems. Second, this project will develop and evaluate changes to the chips and to the applications that will help reduce the demands placed on a chip's shared resources. Specifically, the project will examine ways to organize the shared resources on a chip to more closely match how an application uses these resources. Additionally, this work will propose and evaluate techniques that reduce the amount of unneeded data being incidentally brought onto and stored on a chip. Finally, the project will examine ways to use knowledge about the application to restructure the application in a way that reduces the need to move data to different locations on a chip using the shared wires.