Cross-Layer Error Exploitation for Next Generation SoCs
Cross-Layer Error Exploitation for Next Generation SoCs
批准号:
0702797
负责人:
Nikil Dutt
金额:
$0.0万
依托单位国家:
美国
项目类别:
Continuing Grant
财政年份:
2007
资助国家:
美国
项目状态:
已结题
起止时间:
2007-07-01 至 2011-06-30
中文摘要
标题:下一代soc的跨层误差开发PI名称:Nik DuttPI研究所:UC irvine摘要今天的通信设备(例如,PDA电话,GPS单元等)是通信,视频,图像和语音等许多技术的协同作用。这些技术的共同之处在于,它们表现出(通过设计或其内在性质)对错误的弹性。例如,用户几乎不会注意到图像或视频中的暗像素。另一方面,当无线传输信息时,预计会在空中发生错误,接收器的设计是为了纠正这种错误。相比之下,今天的芯片被设计成无错误的,那些有不可修复缺陷的芯片被丢弃。虽然先进的半导体制造技术允许在小尺寸的芯片上制造更复杂的片上系统(soc),但由于每单位面积的大量晶体管以及它们的邻近性,实现100%无错误的芯片设计在经济上变得不切实际。对于移动应用程序,从100%正确性的范式转变不仅可行,而且似乎不可避免。这个项目的结果将产生一种结构化的、科学的方法来利用复杂soc的多个抽象级别的错误感知。传统上完全不同的(抽象级别特定的)技术的整体集成将允许系统设计人员快速探索复杂的芯片实现,以满足广泛的功率、性能和成本属性。从长远来看,该项目将对生产者-消费者链的两端产生积极影响:芯片制造公司将通过高效制造移动芯片提高生产率并增强竞争力;消费者将受益于低成本的移动芯片,这些芯片允许他们的移动设备运行更长时间,同时确保新兴应用程序的安全和正确执行。
英文摘要
ID: 0702797 Title: Cross-Layer Error Exploitation for Next Generation SoCs PI name: Nik DuttPI Inst: UC IrvineAbstractToday's communication appliances (e.g., PDA phones, GPS units, etc.) are a synergy of many technologies such as communication, video, image, and voice. What is common among these technologies is the fact that they exhibit (either by design, or by their intrinsic nature) a resiliency to errors. The user will hardly notice, for example, a dark pixel in an image or a video. When transmitting information wirelessly, on the other hand, errors are expected to occur over the air and receivers are designed to correct for such errors. By contrast, today's chips are designed to be error free and those chips that have non-fixable defects are discarded. While advanced semiconductor manufacturing technologies allow the fabrication of ever more complex Systems-on-Chip (SoCs) in small die sizes, it becomes economically impractical to achieve a 100% error-free chip design due to the large number of transistors per unit area as well as their proximity. For mobile applications, a paradigm shift away from 100% correctness is not only feasible, but seemingly unavoidable. The outcome of this project will result in a structured and scientific approach to exploit error-awareness across multiple abstraction levels of complex SoCs. A holistic integration of traditionally disparate (abstraction-level specific) techniques will allow system designers to rapidly explore complex chip implementations to meet a wide range of power, performance, and cost attributes. In the long term, this project will positively impact both ends of the producer-consumer chain: chip manufacturing companies will improve their productivity and become more competitive by allowing efficient fabrication of mobile chips; and consumers will benefit through lower cost mobile chips that allow longer operation of their mobile appliances while ensuring safe and correct execution of emerging applications.
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