CSR---SMA: A Design Space Exploration Tool for x86 and x86-64 Multicore Microprocessors

随着对功耗的担忧和硅投资回报的不断减少，业界已经从开发快速单核解决方案转向在单个芯片或封装中集成多个处理核心的设计。处理器的开发工作和相关研究一直依赖于使用精确的功能和时序模拟器。有一个集成的仿真环境是很有用的，它允许在多核微处理器中探索性能、功率和可靠性之间的权衡。所提出的努力解决了目前在这方面的空白，旨在调查、设计、开发和传播这样一个工具系统，用于处理器设计研究和教学。另一个优点是，所提出的仿真框架基于常用的X86和X86-64指令集体系结构（isa）。这允许实现一个完整的系统模拟器，它不仅可以准确地模拟用户级活动，还可以准确地模拟内核级活动，远远超出了常用的用户模式模拟器。X86 isa的使用还允许在底层PC硬件（包括多核平台）上以本机模式执行，从而显著加快对不感兴趣的部分模拟代码的模拟速度。这项工作的结果将是方法论的发展和原型工具的实现，以准确地估计多核微处理器的能量和性能特征。由此产生的工具将通过网络分发给研究小组，促进微处理器设计方面的研究活动，包括考虑能源性能的权衡。

With the emerging concerns of power dissipation and ever diminishing returns on the silicon investment, the industry has moved away from developing fast single-core solutions in favor of designs that integrate muiltiple processing cores within a single chip or package. Processor development efforts and related research have always relied on the use of accurate functional and timing simulators. It is useful to have an integrated simulation environment that permits the exploration of tradeoffs among performance, power and reliability in multicore microprocessors. The proposed effort addresses a current void in this respect and aims to investigate, design, develop and disseminate exactly such a tool system for use in processor design research and pedagogy. As another advantage, the proposed simulation framework is based on the commonly used X86 and X86-64 instruction set architectures (ISAs). This permits the implementation of a full system simulator that goes well beyond the commonly available user-mode simulators in simulating not just the user-level activities but also kernel level activities accurately. The use of the X86 ISAs also permits native mode execution on the underlying PC hardware, including multicore platforms, to significantly speed up simulation over portions of the simulated code that are not of interest. The outcome of this effort will be the development of methodologies and a prototype tool implementation for accurately estimating the energy and performance characteristics of multicore microprocessors. The resulting tool will be distributed to research groups via the web, fostering research activities in microprocessor design, including the consideration of energy-performance tradeoffs.