Inherently Low Power Computer

这个项目主要关注功耗问题，主要是关于在CMOS微处理器中功耗的真正来源是什么，以及如何在更全球的层面上将其降至最低的根本问题。目标是开发和演示支持节能指令集体系结构(PISA)的技术。为此，本文主要完成了以下四个方面的工作：1.开发与工艺无关的芯片功耗模型和度量。2.分析当前的设计，以对技术水平进行基准测试，并识别潜在的耗电处理器子系统。3.开发将减少这些指标的新技术。4.在一个原型CMOSPISA CPU芯片上对这些技术进行了演示。这些新技术将包括门设计级别的方法，但将主要集中在组织和指令集体系结构方法上，这些方法固有地具有较低的功耗要求。S这项研究的最终目标是加深对功率和计算之间关系的科学理解，并开发能够最大限度地减少这两种方式的比率的技术，这些技术可能会广泛影响超大规模集成电路技术的持续发展及其在计算中的成功应用。

This project focuses on the problem of power dissipation, primarily on the fundamental issues of what are the real sources of power dissipation in CMOS microprocessors, and what can be done to minimize it at a more global level. The goal is development and demonstration of techniques that would support Power-efficient Instruction Set Architectures (PISA). For this, there are four major tasks: 1. Developing technology independent models and metrics for power dissipation in CMOS logic. 2. Analyzing current day designs to benchmark the state of the art and to identify processor subsystems that are potential power hogs. 3. Development of new techniques that will reduce these metrics. 4. Demonstration of these techniques in a prototype CMOS PISA CPU chip. These new techniques will include gate design level approaches, but will focus primarily on organizational and instruction set architectural approaches that inherently have a lower power requirement. The end goals of this research s to develop a deeper scientific understanding of the relationship between power and computation, and develop techniques that minimize the ratio of the two ways that can broadly impact the continuing evolution of VLSI Technology and its successful use in computing.