The Design and Evaluation of a High-Performance Capability Mechanism for a VLSI Processor and its Impact on Software Reliability

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A significant portion (70% and upwards, typically) of the cost of a medium to large-scale computing system is in its software. In turn, two-thirds or so of the software cost goes into maintenance--fixing the inevitable program bugs that are discovered later. Capability-based addressing has been suggested as a technique for detecting and avoiding many run-time errors because of its usefulness in enforcing small protection domains, data abstraction and secure module interfaces. Several machines proposed or implemented in the past to support capability-based addressing have been plagued by their abysmally slow speed. The purpose of the research project is to design a high-speed capability mechanism, examine and evaluate its implementation assuming realistic technological constraints. The project starts with the formulation of a simple, yet powerful set of primitives for the capability mechanism, followed by the design and simulation of an architecture using these mechanisms. High-level benchmarks would then be run on the simulator to evaluate the architecture.