SGER: A Virtual Target For Next Generation Hardware Accelerated Multi-Core Systems

SGER：下一代硬件加速多核系统的虚拟目标

• 批准号: 0749508
• 负责人: Tony Givargis
• 金额: $ 20万
• 依托单位: University of California-Irvine
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2008
• 资助国家: 美国
• 起止时间: 2008-01-01 至 2009-12-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=0749508&HistoricalAwards=false
• 关键词: SGER; Virtual; Target; Next; Generation

For years, microprocessor vendors have supplied processors with increasingly faster clock speeds, ensuring the continued growth in the number of embedded products on the market. These embedded products have had a profound impact on the quality of life. Today, and as a result of physical design challenges, the industry finds itself at a turning point, with a shift of emphasis from single-processor core to multi-core systems using Field Programmable Gate Arrays (FPGAs) as means to accelerate compute-bound applications.To obtain desired performance from these new compute platforms, designers are following platform-specific programming and compilation practices. These practices yield non-portable code, and violate the principle of clean separation of function from architecture, reducing the degree of interoperability among developers, tool vendors, and architecture providers.The planned research of virtualizing a multi-core system augmented with FPGA fabric, akin to the concept of virtual machines such as Java VM, provides an abstract and universal underpinning for design and verification of complex embedded software. The research aims to explore and define a parametric virtualization layer providing an abstract view of hardware to the software subsystem and study technologies for configuration checkpointing/rollback and source level debugging support.A virtual platform will enhance and enable research in distributed software, operating systems, compilers, on-chip synthesis, device configuration, debugging, active power management, and FPGA/microprocessor design. It will serve as an important tool in the lecture room and in the hands of students, allowing them to explore, define, and refine the design paradigms of the future.

多年来，微处理器供应商提供的处理器的时钟速度越来越快，确保了市场上嵌入式产品数量的持续增长。这些嵌入式产品对生活质量产生了深远的影响。如今，由于物理设计方面的挑战，行业发现自己正处于一个转折点，重点从单处理器核心转向使用现场可编程门阵列 (FPGA) 的多核系统，作为加速计算密集型应用的手段。为了从这些新的计算平台获得所需的性能，设计人员正在遵循特定于平台的编程和编译实践。这些做法产生了不可移植的代码，并且违反了功能与架构完全分离的原则，降低了开发人员、工具供应商和架构提供商之间的互操作性程度。计划中的虚拟化利用 FPGA 结构增强的多核系统的研究，类似于 Java VM 等虚拟机的概念，为复杂嵌入式软件的设计和验证提供了抽象和通用的基础。该研究旨在探索和定义参数虚拟化层，为软件子系统提供硬件的抽象视图，并研究配置检查点/回滚和源级调试支持的技术。虚拟平台将增强和支持分布式软件、操作系统、编译器、片上综合、设备配置、调试、主动电源管理和 FPGA/微处理器设计方面的研究。它将成为课堂和学生手中的重要工具，让他们能够探索、定义和完善未来的设计范式。