CPA-DA: Low Power Asynchronous Circuits from Traditional Clocked Verilog and ASIC CAD

点击翻译按钮获取中文摘要

Project ID: 0818408Title: Low Power Asynchronous Circuits from Traditional Clocked Verilog and ASIC CADInst: University of UtahPI name: Ken StevensABSTRACTAsynchronous design has been shown to provide substantial power and performance advantages to a wide range of designs when compared to traditional clocked design. This advantage results in extended battery life and energy efficiency. However, asynchronous design (clockless design or ?handshake clocking?) has remained an exotic technology due to its incompatibility with traditional clocked CAD and design methodologies. A fundamental problem to adoption of asynchronous design methods is the inability to characterize and predict performance through static timing analysis, and use timing driven power/performance optimization to place and route these designs. This proposal develops fundamental technology that resolves this roadblock, thus enabling asynchronous design to be integrated into clocked designs and into the clocked CAD tool flows. This opens up a broad capability for designs to operate at higher performance and become more energy efficient. This work is founded on a novel technology called relative timing which uses formal verification techniques to prove both timing and behavioral correctness of asynchronous templates. Timing is now represented as logical constraints. These logical constraints are used to break cyclical sequential circuits into directed acyclic graphs (DAGs). These designs are now directly supported in clocked designs and tool flows as .sdc constraints.There is currently very limited expertise in this technology, so training students must primarily be provided at the university rather than on the job. The combination of a lack of industrial expertise and the high potential of this breakthrough approach has resulted in significant industrial interest. Both Intel, the worlds largest semiconductor firm, and Synopsys, one of the worlds top two design automation companies, are providing funding and mentorship to help commercialize and technology transfer this project. Nanochronous, a startup, is providing CAD tools and research collaboration. The involvement of under represented minorities are also a focus of this project as a female engineer will be supported by this research. A workshop will be formed to disseminate the results of this work. Finally this project will work collaboratively with a sister grant developing Network-on-Chip technology to prove the simplicity of adopting this work into broader applications.