CPA-DA: Low Power Asynchronous Circuits from Traditional Clocked Verilog and ASIC CAD

CPA-DA：来自传统时钟 Verilog 和 ASIC CAD 的低功耗异步电路

• 批准号: 0810408
• 负责人: Kenneth Stevens
• 金额: $ 45.01万
• 依托单位: University of Utah
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2008
• 资助国家: 美国
• 起止时间: 2008-08-01 至 2011-07-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=0810408&HistoricalAwards=false
• 关键词: CPA; DA; Low; Power; Asynchronous

Project ID: 0818408Title: Low Power Asynchronous Circuits from Traditional Clocked Verilog and ASIC CADInst: University of UtahPI name: Ken StevensABSTRACTAsynchronous design has been shown to provide substantial power and performance advantages to a wide range of designs when compared to traditional clocked design. This advantage results in extended battery life and energy efficiency. However, asynchronous design (clockless design or ?handshake clocking?) has remained an exotic technology due to its incompatibility with traditional clocked CAD and design methodologies. A fundamental problem to adoption of asynchronous design methods is the inability to characterize and predict performance through static timing analysis, and use timing driven power/performance optimization to place and route these designs. This proposal develops fundamental technology that resolves this roadblock, thus enabling asynchronous design to be integrated into clocked designs and into the clocked CAD tool flows. This opens up a broad capability for designs to operate at higher performance and become more energy efficient. This work is founded on a novel technology called relative timing which uses formal verification techniques to prove both timing and behavioral correctness of asynchronous templates. Timing is now represented as logical constraints. These logical constraints are used to break cyclical sequential circuits into directed acyclic graphs (DAGs). These designs are now directly supported in clocked designs and tool flows as .sdc constraints.There is currently very limited expertise in this technology, so training students must primarily be provided at the university rather than on the job. The combination of a lack of industrial expertise and the high potential of this breakthrough approach has resulted in significant industrial interest. Both Intel, the worlds largest semiconductor firm, and Synopsys, one of the worlds top two design automation companies, are providing funding and mentorship to help commercialize and technology transfer this project. Nanochronous, a startup, is providing CAD tools and research collaboration. The involvement of under represented minorities are also a focus of this project as a female engineer will be supported by this research. A workshop will be formed to disseminate the results of this work. Finally this project will work collaboratively with a sister grant developing Network-on-Chip technology to prove the simplicity of adopting this work into broader applications.

项目编号：0818408职务：从传统时钟Verilog和ASIC的低功耗异步电路CADInst：犹他大学PI姓名：Ken Stevens摘要同步设计已被证明提供大量的功率和性能优势，以广泛的设计时，与传统的时钟设计。这一优势可延长电池寿命并提高能效。然而，异步设计（无时钟设计或？握手计时？）由于其与传统的时钟CAD和设计方法不兼容，采用异步设计方法的一个基本问题是无法通过静态时序分析来表征和预测性能，并且无法使用时序驱动的功率/性能优化来放置和布线这些设计。该提案开发了解决这一障碍的基础技术，从而使异步设计能够集成到时钟设计和时钟CAD工具流程中。这为设计以更高的性能运行并变得更节能开辟了广泛的能力。这项工作是建立在一个新的技术称为相对定时，使用正式的验证技术来证明异步模板的时间和行为的正确性。时间现在被表示为逻辑约束。这些逻辑约束用于将循环时序电路分解为有向非循环图（DAG）。这些设计现在直接支持时钟设计和工具流程作为.sdc约束。目前在这项技术方面的专业知识非常有限，因此必须主要在大学而不是在工作中提供培训。由于缺乏工业专门知识，加上这种突破性方法的巨大潜力，引起了工业界的极大兴趣。世界上最大的半导体公司英特尔和世界上两大设计自动化公司之一的Synopsys都在提供资金和指导，以帮助该项目的商业化和技术转让。初创公司Nanoparticle正在提供CAD工具和研究合作。代表性不足的少数民族的参与也是该项目的一个重点，因为这项研究将支持一名女工程师。将举办一个讲习班，传播这项工作的成果。最后，本项目将与开发片上网络技术的姐妹基金合作，以证明将这项工作应用于更广泛的应用的简单性。