CPA-CPL: Compiler and Software Solutions for the Memory Bottleneck on Multicore

CPA-CPL：针对多核内存瓶颈的编译器和软件解决方案

• 批准号: 0811587
• 负责人: Zhiyuan Li
• 金额: $ 30万
• 依托单位: Purdue University
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2008
• 资助国家: 美国
• 起止时间: 2008-08-01 至 2012-07-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=0811587&HistoricalAwards=false
• 关键词: CPA; CPL; Compiler; Software; Solutions

Virtually every high-performance processor today has multiple processingunits (also known as cores) on a single chip. Such multicore hardwaredesigns present opportunities for significant performance gains, byprocessing multiple tasks simultaneously, thus enabling novelcompute-intensive applications. Executing multiple tasks on a single chiprequires data to be transported in and out of the chip at a rate whichoften exceeds current hardware capability. Consequently, realizing theperformance potential of current multicore processors requires novelsolutions to the memory bottleneck problem. This project investigatessoftware solutions to alleviate the memory bottleneck. The main idea is touse program transformation tools (also called compilers) to restructureprograms so that they can best utilize deep and complex memoryhierarchies, and to account for such hardware optimizations as prefetchingand shared caches.This project investigates novel programming models and constructs forscalable multicore processors, and compiler techniques to support suchmodels and constructs. It also aims to develop a runtime infrastructurefor message passing aggregates to support such models and constructs onclusters of multicore processors. Software developments are augmented byanalytical models that guide application development and compileroptimizations. Software techniques and theoretical models are validatedfor performance and scalability on platforms ranging from multicoredesktop machines to clusters of multicore processors.

如今，几乎每个高性能处理器在一块芯片上都有多个处理单元(也称为核心)。这种多核硬件设计通过同时处理多个任务，提供了显著提高性能的机会，从而支持新的计算密集型应用程序。在单个芯片上执行多个任务需要以超过当前硬件能力的速度将数据传输进和传出芯片。因此，实现当前多核处理器的性能潜力需要新的内存瓶颈问题解决方案。本项目研究缓解内存瓶颈的软件解决方案。该项目的主要思想是使用程序转换工具(也称为编译器)来重构程序，使其能够最大限度地利用深度和复杂的存储层次结构，并考虑预取和共享缓存等硬件优化。本项目研究可扩展的多核处理器的新颖编程模型和结构，以及支持这些模型和结构的编译器技术。它还旨在为消息传递聚合开发一个运行时基础设施，以支持多核处理器集群上的此类模型和构造。软件开发被指导应用程序开发和编译器优化的分析模型所增强。软件技术和理论模型在从多核台式机到多核处理器集群的各种平台上得到了性能和可扩展性的验证。