CPA-CPL: Compiler and Software Solutions for the Memory Bottleneck on Multicore

实际上，今天每个高性能处理器在单个芯片上都有多个处理单元（也称为核心）。这种多核硬件设计通过同时处理多个任务，为显著提高性能提供了机会，从而实现了新的计算密集型应用程序。在单个芯片上执行多个任务要求数据以超出当前硬件能力的速率进出芯片。因此，实现当前多核处理器的性能潜力需要新的解决方案来解决内存瓶颈问题。该项目研究了缓解内存瓶颈的软件解决方案。其主要思想是使用程序转换工具（也称为编译器）来重构程序，以便它们能够最好地利用深层和复杂的内存层次结构，并考虑诸如预取和共享缓存之类的硬件优化。该项目研究可扩展多核处理器的新颖编程模型和结构，以及支持此类模型和结构的编译器技术。它还旨在为消息传递聚合开发一个运行时基础设施，以支持这种模型和多核处理器集群上的构造。软件开发通过指导应用程序开发和编译器优化的分析模型得到增强。软件技术和理论模型在从多核桌面机器到多核处理器集群的平台上进行了性能和可扩展性验证。

Virtually every high-performance processor today has multiple processingunits (also known as cores) on a single chip. Such multicore hardwaredesigns present opportunities for significant performance gains, byprocessing multiple tasks simultaneously, thus enabling novelcompute-intensive applications. Executing multiple tasks on a single chiprequires data to be transported in and out of the chip at a rate whichoften exceeds current hardware capability. Consequently, realizing theperformance potential of current multicore processors requires novelsolutions to the memory bottleneck problem. This project investigatessoftware solutions to alleviate the memory bottleneck. The main idea is touse program transformation tools (also called compilers) to restructureprograms so that they can best utilize deep and complex memoryhierarchies, and to account for such hardware optimizations as prefetchingand shared caches.This project investigates novel programming models and constructs forscalable multicore processors, and compiler techniques to support suchmodels and constructs. It also aims to develop a runtime infrastructurefor message passing aggregates to support such models and constructs onclusters of multicore processors. Software developments are augmented byanalytical models that guide application development and compileroptimizations. Software techniques and theoretical models are validatedfor performance and scalability on platforms ranging from multicoredesktop machines to clusters of multicore processors.