CPA-CPL: Compiler and Software Solutions for the Memory Bottleneck on Multicore

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Virtually every high-performance processor today has multiple processingunits (also known as cores) on a single chip. Such multicore hardwaredesigns present opportunities for significant performance gains, byprocessing multiple tasks simultaneously, thus enabling novelcompute-intensive applications. Executing multiple tasks on a single chiprequires data to be transported in and out of the chip at a rate whichoften exceeds current hardware capability. Consequently, realizing theperformance potential of current multicore processors requires novelsolutions to the memory bottleneck problem. This project investigatessoftware solutions to alleviate the memory bottleneck. The main idea is touse program transformation tools (also called compilers) to restructureprograms so that they can best utilize deep and complex memoryhierarchies, and to account for such hardware optimizations as prefetchingand shared caches.This project investigates novel programming models and constructs forscalable multicore processors, and compiler techniques to support suchmodels and constructs. It also aims to develop a runtime infrastructurefor message passing aggregates to support such models and constructs onclusters of multicore processors. Software developments are augmented byanalytical models that guide application development and compileroptimizations. Software techniques and theoretical models are validatedfor performance and scalability on platforms ranging from multicoredesktop machines to clusters of multicore processors.