CPA-CPL: Compiler and Software Solutions for the Memory Bottleneck on Multicore

CPA-CPL：针对多核内存瓶颈的编译器和软件解决方案

• 批准号: 0811587
• 负责人: Zhiyuan Li
• 金额: $ 30万
• 依托单位: Purdue University
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2008
• 资助国家: 美国
• 起止时间: 2008-08-01 至 2012-07-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=0811587&HistoricalAwards=false
• 关键词: CPA; CPL; Compiler; Software; Solutions

Virtually every high-performance processor today has multiple processingunits (also known as cores) on a single chip. Such multicore hardwaredesigns present opportunities for significant performance gains, byprocessing multiple tasks simultaneously, thus enabling novelcompute-intensive applications. Executing multiple tasks on a single chiprequires data to be transported in and out of the chip at a rate whichoften exceeds current hardware capability. Consequently, realizing theperformance potential of current multicore processors requires novelsolutions to the memory bottleneck problem. This project investigatessoftware solutions to alleviate the memory bottleneck. The main idea is touse program transformation tools (also called compilers) to restructureprograms so that they can best utilize deep and complex memoryhierarchies, and to account for such hardware optimizations as prefetchingand shared caches.This project investigates novel programming models and constructs forscalable multicore processors, and compiler techniques to support suchmodels and constructs. It also aims to develop a runtime infrastructurefor message passing aggregates to support such models and constructs onclusters of multicore processors. Software developments are augmented byanalytical models that guide application development and compileroptimizations. Software techniques and theoretical models are validatedfor performance and scalability on platforms ranging from multicoredesktop machines to clusters of multicore processors.

实际上，如今的每个高性能处理器都有一个芯片上的多个加工工具（也称为核心）。这样的多项硬件装饰品为大量绩效增长提供了机会，同时通过多个任务进行了处理，从而实现了新颖的量强度应用程序。以通常超过当前硬件功能的速率，在单个芯片数据中执行多个任务。因此，意识到当前多核算处理器的性能潜力需要小说解决内存瓶颈问题。该项目调查解决方案，以减轻内存瓶颈。主要思想是touse程序转换工具（也称为编译器）来重组程序，以便它们可以最好地利用深层和复杂的内存层次结构，并考虑到预购和共享缓存等硬件优化。该项目调查新颖的编程模型，并构建了可扩展的多功能处理器，以及支持该构造的典型的多功能处理器，以及支持这样的构造和构造。它还旨在开发一个运行时基础架构，用于传递汇总的消息，以支持此类模型和构造多层处理器的闭合器。软件开发是增强的，可以指导应用程序开发和编译量化的模型。软件技术和理论模型均已验证，以验证从多层计算机到多层处理器群的平台上的性能和可伸缩性。