Parametric Compiler Optimization for Multi-Core Architectures

多核架构的参数编译器优化

• 批准号: 0702245
• 负责人: Zhiyuan Li
• 金额: $ 27.5万
• 依托单位: Purdue University
• 依托单位国家: 美国
• 项目类别: Continuing Grant
• 财政年份: 2007
• 资助国家: 美国
• 起止时间: 2007-08-01 至 2012-07-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=0702245&HistoricalAwards=false
• 关键词: Parametric; Compiler; Optimization; Multi; Core

The power dissipation problem is causing a shift of commodity microprocessor architectures towards multi-core chips. By industry's forecast, the number of cores, also known as computation engines, on a single chip is to increase at an exponential rate at least for the decade ahead of us. How to use multiple processors simultaneously for a single application problem is no longer an issue unique to the supercomputing domain but also to software that runs on commodity microprocessors. This project investigates the execution model, task scheduling methods and compiler techniques to achieve the goal of efficient use of multiple processors on a single chip.The focus of this project concerns the mapping between program operations and the complex architectures which offer parallelism and data locality in various forms on a single chip. Such intricate parallelism and localities make optimal deployment of computational tasks difficult for programmers to manage without associated compiler support and related programming tools. A critical research objective of this proposal is to design and implement a parametric approach to parallel code generation and scheduling on multi-core architectures. Based on this approach, an adaptive scheme for computation offloading is employed on heterogeneous multi-core (HMC) chips. The scheme is novel in two major aspects. Firstly, it has a single unified framework for several different system architectures of HMC, abstracting various architecture differences by a set of parameters plugged into a task partitioning mathematical system. Secondly, the code it generates, as the result of task partitioning, has the ability to adapt to the change in the program's execution context, including the data sizes and the execution options, which is often unpredictable at compile time.

功率耗散问题是导致商品微处理器架构向多核芯片的转移。根据行业的预测，一个芯片上的核心数量（也称为计算引擎）的数量至少要以指数级的速度提高。如何同时将多个处理器用于单个应用程序问题不再是超级计算域所特有的问题，而是在商品微处理器上运行的软件。该项目研究了执行模型，任务调度方法和编译器技术，以实现在单个芯片上有效使用多个处理器的目标。该项目的重点涉及程序操作与复杂体系结构之间的映射，这些构图在单个芯片上提供了各种形式的并行性架构。这种错综复杂的并行性和地方使程序员难以在没有相关编译器支持和相关编程工具的情况下管理计算任务的最佳部署。该提案的一个关键研究目标是设计和实施一种参数方法，以对多核体系结构进行并行代码生成和计划。基于这种方法，在异质多核（HMC）芯片上采用了用于计算卸载的自适应方案。该方案在两个主要方面是新颖的。首先，它具有用于HMC的几个不同系统体系结构的单个统一框架，通过插入任务分配数学系统的一组参数来抽象各种体系结构差异。其次，由于任务分配而产生的代码可以适应程序执行上下文中的更改，包括数据尺寸和执行选项，在编译时通常无法预测。