Parametric Compiler Optimization for Multi-Core Architectures

多核架构的参数编译器优化

• 批准号: 0702245
• 负责人: Zhiyuan Li
• 金额: $ 27.5万
• 依托单位: Purdue University
• 依托单位国家: 美国
• 项目类别: Continuing Grant
• 财政年份: 2007
• 资助国家: 美国
• 起止时间: 2007-08-01 至 2012-07-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=0702245&HistoricalAwards=false
• 关键词: Parametric; Compiler; Optimization; Multi; Core

The power dissipation problem is causing a shift of commodity microprocessor architectures towards multi-core chips. By industry's forecast, the number of cores, also known as computation engines, on a single chip is to increase at an exponential rate at least for the decade ahead of us. How to use multiple processors simultaneously for a single application problem is no longer an issue unique to the supercomputing domain but also to software that runs on commodity microprocessors. This project investigates the execution model, task scheduling methods and compiler techniques to achieve the goal of efficient use of multiple processors on a single chip.The focus of this project concerns the mapping between program operations and the complex architectures which offer parallelism and data locality in various forms on a single chip. Such intricate parallelism and localities make optimal deployment of computational tasks difficult for programmers to manage without associated compiler support and related programming tools. A critical research objective of this proposal is to design and implement a parametric approach to parallel code generation and scheduling on multi-core architectures. Based on this approach, an adaptive scheme for computation offloading is employed on heterogeneous multi-core (HMC) chips. The scheme is novel in two major aspects. Firstly, it has a single unified framework for several different system architectures of HMC, abstracting various architecture differences by a set of parameters plugged into a task partitioning mathematical system. Secondly, the code it generates, as the result of task partitioning, has the ability to adapt to the change in the program's execution context, including the data sizes and the execution options, which is often unpredictable at compile time.

功耗问题导致商品微处理器架构向多核芯片的转变。根据业界预测，至少在未来十年内，单个芯片上的核心（也称为计算引擎）数量将以指数级速度增长。如何同时使用多个处理器解决单个应用问题不再是超级计算领域独有的问题，也是在商品微处理器上运行的软件所独有的问题。该项目研究了在单芯片上有效使用多处理器的执行模型、任务调度方法和编译技术，重点关注程序操作与复杂体系结构之间的映射，这些复杂体系结构在单芯片上以各种形式提供并行性和数据局部性。这种复杂的并行性和局部性使得程序员在没有相关编译器支持和相关编程工具的情况下难以管理计算任务的最佳部署。该提案的一个关键研究目标是设计和实现一个参数化的方法来并行代码生成和调度多核架构。在此基础上，提出了一种基于异构多核（HMC）芯片的自适应计算卸载方案。该方案在两个主要方面是新颖的。首先，它有一个统一的框架，为几个不同的系统架构的HMC，抽象的各种体系结构的差异，一组参数插入到一个任务划分的数学系统。其次，它生成的代码，作为任务划分的结果，有能力适应程序执行上下文的变化，包括数据大小和执行选项，这在编译时通常是不可预测的。