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Parametric Compiler Optimization for Multi-Core Architectures

Parametric Compiler Optimization for Multi-Core Architectures
多核架构的参数编译器优化
批准号:
0702245
负责人:
Zhiyuan Li
金额:
$27.5万
依托单位:
依托单位国家:
美国
项目类别:
Continuing Grant
财政年份:
2007
资助国家:
美国
项目状态:
已结题
起止时间:
2007-08-01 至 2012-07-31

项目摘要

项目成果

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中文摘要
翻译
功耗问题导致了商用微处理器架构向多核芯片的转变。根据业界预测,至少在未来十年,单个芯片上的核心(也称为计算引擎)数量将以指数级速度增长。如何在单个应用程序中同时使用多个处理器的问题不再是超级计算领域所独有的问题,而是运行在商用微处理器上的软件所特有的问题。本课题研究了执行模型、任务调度方法和编译技术,以实现单芯片上多处理器高效使用的目标。该项目的重点关注程序操作和复杂架构之间的映射,这些架构在单个芯片上以各种形式提供并行性和数据局部性。这种复杂的并行性和位置使得程序员很难在没有相关编译器支持和相关编程工具的情况下管理计算任务的最佳部署。本提案的一个关键研究目标是设计和实现一种参数化方法来并行代码生成和调度多核架构。在此基础上,在异构多核(HMC)芯片上采用了一种自适应的计算卸载方案。该方案在两个主要方面是新颖的。首先,它为HMC的几种不同的系统架构提供了一个统一的框架,通过将一组参数插入到任务划分的数学系统中来抽象各种架构的差异。其次,作为任务分区的结果,它生成的代码有能力适应程序执行上下文的变化,包括数据大小和执行选项,这在编译时通常是不可预测的。
英文摘要
The power dissipation problem is causing a shift of commodity microprocessor architectures towards multi-core chips. By industry's forecast, the number of cores, also known as computation engines, on a single chip is to increase at an exponential rate at least for the decade ahead of us. How to use multiple processors simultaneously for a single application problem is no longer an issue unique to the supercomputing domain but also to software that runs on commodity microprocessors. This project investigates the execution model, task scheduling methods and compiler techniques to achieve the goal of efficient use of multiple processors on a single chip.The focus of this project concerns the mapping between program operations and the complex architectures which offer parallelism and data locality in various forms on a single chip. Such intricate parallelism and localities make optimal deployment of computational tasks difficult for programmers to manage without associated compiler support and related programming tools. A critical research objective of this proposal is to design and implement a parametric approach to parallel code generation and scheduling on multi-core architectures. Based on this approach, an adaptive scheme for computation offloading is employed on heterogeneous multi-core (HMC) chips. The scheme is novel in two major aspects. Firstly, it has a single unified framework for several different system architectures of HMC, abstracting various architecture differences by a set of parameters plugged into a task partitioning mathematical system. Secondly, the code it generates, as the result of task partitioning, has the ability to adapt to the change in the program's execution context, including the data sizes and the execution options, which is often unpredictable at compile time.
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XPS:EXPL:DSD: Language Abstraction, Annotation, Compiler Optimization Techniques for Efficient CFD Computation
  • 批准号:
    1533822
  • 项目类别:
    Standard Grant
  • 资助金额:
    $27.32万
  • 财政年份:
    2015
  • 负责人:
    Zhiyuan Li
  • 依托单位:
CSR:Small:New Slicing Techniques for Program Parallelization
  • 批准号:
    0915414
  • 项目类别:
    Standard Grant
  • 资助金额:
    $42.91万
  • 财政年份:
    2009
  • 负责人:
    Zhiyuan Li
  • 依托单位:
CRI: Planning - A Testbed for Compiler-supported Scalable Error Monitoring and Diagnosis for Reliable and Secure Sensor Networks
  • 批准号:
    0751101
  • 项目类别:
    Standard Grant
  • 资助金额:
    $4.89万
  • 财政年份:
    2008
  • 负责人:
    Zhiyuan Li
  • 依托单位:
CPA-CPL: Compiler and Software Solutions for the Memory Bottleneck on Multicore
  • 批准号:
    0811587
  • 项目类别:
    Standard Grant
  • 资助金额:
    $30.0万
  • 财政年份:
    2008
  • 负责人:
    Zhiyuan Li
  • 依托单位:
海外基金