Parametric Compiler Optimization for Multi-Core Architectures

多核架构的参数编译器优化

• 批准号: 0702245
• 负责人: Zhiyuan Li
• 金额: $ 27.5万
• 依托单位: Purdue University
• 依托单位国家: 美国
• 项目类别: Continuing Grant
• 财政年份: 2007
• 资助国家: 美国
• 起止时间: 2007-08-01 至 2012-07-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=0702245&HistoricalAwards=false
• 关键词: Parametric; Compiler; Optimization; Multi; Core

The power dissipation problem is causing a shift of commodity microprocessor architectures towards multi-core chips. By industry's forecast, the number of cores, also known as computation engines, on a single chip is to increase at an exponential rate at least for the decade ahead of us. How to use multiple processors simultaneously for a single application problem is no longer an issue unique to the supercomputing domain but also to software that runs on commodity microprocessors. This project investigates the execution model, task scheduling methods and compiler techniques to achieve the goal of efficient use of multiple processors on a single chip.The focus of this project concerns the mapping between program operations and the complex architectures which offer parallelism and data locality in various forms on a single chip. Such intricate parallelism and localities make optimal deployment of computational tasks difficult for programmers to manage without associated compiler support and related programming tools. A critical research objective of this proposal is to design and implement a parametric approach to parallel code generation and scheduling on multi-core architectures. Based on this approach, an adaptive scheme for computation offloading is employed on heterogeneous multi-core (HMC) chips. The scheme is novel in two major aspects. Firstly, it has a single unified framework for several different system architectures of HMC, abstracting various architecture differences by a set of parameters plugged into a task partitioning mathematical system. Secondly, the code it generates, as the result of task partitioning, has the ability to adapt to the change in the program's execution context, including the data sizes and the execution options, which is often unpredictable at compile time.

功耗问题正导致商用微处理器体系结构转向多核芯片。根据行业预测，至少在未来十年，单个芯片上的核心数量将以指数速度增长，也被称为计算引擎。如何同时使用多个处理器来解决单个应用问题，不再是超级计算领域独有的问题，也是运行在商用微处理器上的软件所独有的问题。该项目研究了执行模型、任务调度方法和编译器技术，以达到在一块芯片上高效使用多个处理器的目标，该项目的重点是程序操作与在单芯片上提供各种形式的并行性和数据局部性的复杂体系结构之间的映射。这种错综复杂的并行性和局部性使得程序员在没有关联的编译器支持和相关编程工具的情况下很难管理计算任务的优化部署。该方案的一个关键研究目标是设计和实现一种在多核体系结构上并行代码生成和调度的参数方法。基于该方法，在异构型多核(HMC)芯片上采用了一种自适应计算卸载方案。该计划在两个主要方面是新颖的。首先，对于HMC的几种不同的系统架构，它有一个单一的统一框架，通过插入到任务划分数学系统中的一组参数来抽象各种架构差异。其次，作为任务划分的结果，它生成的代码能够适应程序执行上下文的变化，包括数据大小和执行选项，这在编译时通常是不可预测的。