CPA-DA: Probalistic wearout in Nanoscale CMOS: analysis, monitoring and optimiazation

提案编号：0811612 PI：西尔维斯特，丹尼斯标题：CPA-DA：纳米级CMOS中的可能磨损：分析、监控和优化机构：密歇根大学安娜堡分校摘要PI建议开发计算机辅助设计工具和电路设计技术，以分析、监控和提高极端规模CMOS（即，低于45 nm），存在显著水平的可变性。期望的结果是一种内聚方法，该方法通过在设计时更好的估计（导致减少设计裕量，从而减少设计时间和成本）和基于电路的技术来提高芯片寿命，该技术能够在给定管芯的寿命期间进行制造后监测和提高鲁棒性。这项工作的主要组成部分包括：1）统计地确定预期的芯片级可靠性的工具，2）理论上严格的方法，其使用晶片上的少量硅后测量来改善较大芯片组的可靠性/性能特性，3）新的超紧凑芯片上传感器，其以低开销和与现代设计方法的兼容性来监视可靠性机制，4）基于芯片的静态电流汲取以监视磨损的新颖间接测量方案，5）对抗非常高的固有故障率的设计风格（例如，1/1000的设备发生故障）。所提出的策略，以提高可靠性，在高度可变的纳米级CMOS将促进持续改进的性能和鲁棒性的集成电路-半导体和信息技术的持续发展的必要条件。特别是，更高的功能和参数产量将使成本更低，这将在很大程度上有利于无线/移动的等成本受限的市场。这项工作的影响将通过利用有前途的本科研究人员，通过课程的改进，并通过行业互动，通过类项目指导来增强。在研究生阶段，这项研究将涉及几个学生攻读博士和硕士？的学位，直接培训他们在这一领域进行研究。根据拟议的研究开发的知识将被纳入超大规模集成电路CAD和电路课程在本科和研究生水平。在系一级、会议和其他大学举办的研讨会和辅导班将在传播从这项研究中获得的知识方面发挥重要作用，沿着在顶级期刊和国际会议上的传统出版物。

Proposal No: 0811612PI: Sylvester, DennisTitle: CPA-DA: Probabilistic wearout in Nanoscale CMOS: analysis, monitoring and optimizationInstitution: University of Michigan Ann ArborABSTRACTThe PIs propose the development of computer-aided design tools and circuit design techniques to analyze, monitor, and improve the reliability of integrated circuits in extremely scaled CMOS (i.e., sub-45nm) with significant levels of variability present. The desired outcome is a cohesive approach that improves chip lifetimes via both better estimation at design time (leading to reduced design margining, and therefore design times and costs) and circuit-based techniques that enable post-fabrication monitoring and improvement of robustness during the lifetime of a given die. The key components of this work include: 1) a tool that statistically determines expected chip-level reliability, 2) a theoretically rigorous approach that uses a small number of post-silicon measurements on a wafer to improve the reliability/performance characteristics of a larger set of chips, 3) new ultra-compact on-chip sensors to monitor reliability mechanisms with low overhead and compatibility with modern design methodologies, 4) a novel indirect measurement scheme based on the quiescent current draw of a chip to monitor for wearout, 5) design styles to combat very high intrinsic failure rates (e.g., 1 in 1000 devices fail). The proposed strategy to improve reliability in highly variable nanoscale CMOS will facilitate sustained improvement in the performance and robustness of integrated circuits - a necessary condition for the continued evolution of semiconductor and information technology. In particular, higher functional and parametric yields will enable lower costs, which will largely benefit cost-constrained markets such as wireless/mobile. The impact of this work will be enhanced by leveraging promising undergraduate researchers, through improvements in curriculum, and through industrial interaction via class project mentoring. At the graduate level, this research will involve several students pursuing doctoral and master?s degrees, training them directly to conduct research in this area. The knowledge developed under the proposed research will be incorporated in VLSI CAD and circuits courses at both the undergraduate and graduate levels. Seminars and tutorials presented at the departmental level, at conferences, and at other universities will play an important role in disseminating the knowledge gained from this research, along with conventional publication in top journals and international conferences.