SGER: Hybrid MIMO Sphere Decoder VLSI Architecture

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The objective of this research is to advance multi-antenna wireless communication devices by providing signal processing hardware that can adapt to varying operating conditions. The approach is based on layered optimization that spans signal processing algorithms, hardware architectures, digital circuits, and the underlying semiconductor devices. The goal is to demonstrate improvements of several orders of magnitude in both deployed algorithm complexity and hardware cost.With respect to intellectual merit, this project provides a hardware solution that leverages the fundamental tradeoff between diversity and spatial-multiplexing in multi-antenna wireless channels. High algorithm complexity limits current practical systems to 4-by-4 antenna arrays and a single operating mode. This work supports adaptive antenna arrays (up to 16-by-16) and multiple operating modes, with reduced hardware cost. This flexibility is being realized in hardware, resulting in a 100 times improvement in energy efficiency compared to general-purpose processors. An objective is to use silicon area more effectively to provide higher data rates, improved services to mobile devices, and access to a variety of existing and new applications.With respect to broader impacts, the multidisciplinary nature of the proposed work naturally stimulates collaboration among circuit design, signal processing, and communications areas. This collaboration has the potential to provide new insights for practical algorithm development and hardware design strategies. The results are being integrated into the curriculum to overcome the artificial and historic boundaries between these disciplines. In the future, concepts from this work are expected to be transformed to parallel data processing in healthcare systems. The potential long-term social and economic impact of this work includes sustaining the evolution and growth of semiconductor technology to new application domains.