ACED Fab: Runtime Reconfigurable Array (RTRA) Technology for AI/ML

ACED Fab：适用于 AI/ML 的运行时可重构阵列 (RTRA) 技术

• 批准号: 2315295
• 负责人: Dejan Markovic
• 金额: $ 50万
• 依托单位: University of California-Los Angeles
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2023
• 资助国家: 美国
• 起止时间: 2023-07-01 至 2026-06-30
• 项目状态: 未结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=2315295&HistoricalAwards=false
• 关键词: ACED; Fab; Runtime; Reconfigurable; Array

Fast-developing artificial intelligence (AI) and machine learning (ML) models, which double in complexity every 3-4 months, outpace the development of underlying hardware accelerators for AI/ML. Presently, deployment of AI/ML algorithms is limited by hardware that lacks agility and energy efficiency to support new models, limiting progress in science and engineering applications (e.g., next-generation wireless systems). Hardware adaptation without sacrificing energy efficiency is needed to embed AI/ML models into mobile, edge, and cloud devices. Researchers from the University of California, Los Angeles (UCLA) along with National Taiwan University (NTU) and Taiwan Semiconductor Research Institute (TSRI) are joining together to develop and demonstrate proof-of-concept runtime reconfigurable array (RTRA) technology that addresses the issues of energy efficiency and agility in existing devices. RTRA is a forward-looking architecture, where agile AI/ML hardware pipelines are dynamically reconfigured to embed new models or respond to dynamic environments. Such technology requires finely balanced hardware and software. Simple hardware leads to complex software (e.g., Field Programmable Gate Array, or FPGA) and simple software leads to complex hardware (e.g., Central Processing Unit, or CPU). RTRA balances hardware and software to enable spatial and temporal flexibility. Spatio-temporal randomization of RTRA is more immune against physical attacks, reverse engineering, supply chain and hardware Trojans, due to its unique software/hardware approach. The project team will use system-based cross-disciplinary approach to address several key challenges of RTRA: 1) efficient programming paradigm, 2) 2D scheduling of hardware resources, 3) high-level abstraction that can fulfill low-level hardware potential, 4) multi-program tenancy, and 5) reconfiguration speed at the pipeline level (tens of clock cycles).The project aims to develop a runtime reconfigurable array technology for AI/ML that provides program switch decisions at sub-microsecond scale, supports multiple active programs, multi-size compile, and priority handling. RTRA should be programmable from high-level languages such as C or Python. Online hardware scheduling enables rapid runtime reconfiguration. The hardware agility is enabled by online dynamic multi-program hardware scheduling, domain-specific reconfigurable array and area-efficient interconnect for multi-program tenancy and flexible data interfaces. The hardware includes embedded processor for control, system memory, and data interfaces for heterogeneous system integration. The energy efficient processing (10x better than FPGA, with another ~10x higher resource utilization) is a significant improvement over existing FPGA AI accelerators, while adding spatiotemporal dynamics for advanced AI/ML models. An internally developed software toolchain (from C or Python to soft binary) will be made available to compile and test various AI/ML use cases. The project team brings unique capability to develop, test, and utilize an integrated system. Broadly, the technology enables rapid deployment of newly developed algorithms, accelerating the deployment of innovative applications. Further, the ability to quickly repurpose hardware provides an opportunity to utilize “dark silicon” and potentially displace today’s fixed-function hardware accelerators with energy-efficient runtime reconfigurable fabric. RTRA technology is envisioned to meet the needs of future communications and AI/ML workloads, with readily accessible C or Python programming. The project leverages the complementary academic talent in the U.S. and Taiwan to impact semiconductor engineering and education.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.

快速发展的人工智能（AI）和机器学习（ML）模型，每3-4个月复杂性每3-4个月两倍，超过了AI/ML的基础硬件加速器的开发。目前，AI/ML算法的部署受到缺乏敏捷性和能源效率支持新模型的硬件的限制，从而限制了科学和工程应用程序的进展（例如，下一代无线系统）。需要在不牺牲能源效率的情况下进行硬件改编才能将AI/ML模型嵌入到移动，边缘和云设备中。加州大学，洛杉矶分校（UCLA）以及台湾大学（NTU）和台湾半导体研究所（TSRI）的研究人员正在共同开发和展示可验证的运行时重新配置阵列（RTRA）技术，以解决现有设备中能源效率和敏捷性问题。 RTRA是一种前瞻性的体系结构，敏捷的AI/ML硬件管道被动态重新配置以嵌入新模型或响应动态环境。这样的技术需要精细平衡的硬件和软件。简单的硬件会导致复杂的软件（例如现场可编程门数组或FPGA）和简单的软件会导致复杂的硬件（例如中央处理单元或CPU）。 RTRA平衡硬件和软件以实现空间和临时的灵活性。由于其独特的软件/硬件方法，RTRA的时空随机性是针对物理攻击，逆向工程，供应链和硬件特洛伊木马的更多免疫学。 The project team will use system-based cross-disciplinary approach to address several key challenges of RTRA: 1) efficient programming paradigm, 2) 2D scheduling of hardware resources, 3) high-level abstraction that can fulfill low-level hardware potential, 4) multi-program tenancy, and 5) reconfiguration speed at the pipeline level (tens of clock cycles).The project aims to develop a runtime reconfigurable array technology对于AI/ML，可以在子微秒刻度上提供程序切换决策，支持多个活动程序，多尺寸的编译和优先处理。应该从C或Python等高级语言中进行编程。在线硬件计划可以快速运行时重新配置。硬件敏捷性是通过在线动态多程序硬件调度，特定于域特异性的可重构数组和区域效率的互连的，用于多程序租赁和灵活的数据接口。该硬件包括用于控制，系统内存和用于异质系统集成的数据接口的嵌入式处理器。节能处理（比FPGA好10倍，另一个〜10倍的资源利用率）是对现有FPGA AI加速器的显着改善，同时为高级AI/ML模型添加了时空动力学。内部开发的软件工具链（从C或Python到软二进制）将可用于编译和测试各种AI/ML用例。项目团队具有开发，测试和利用集成系统的独特功能。从广义上讲，该技术可以快速部署新开发的算法，从而加速了创新应用的部署。此外，快速改革硬件的能力为利用“深色硅”的机会提供了机会，并有可能用可节能的运行时重新配置来取代当今的固定功能硬件加速器。设想RTRA技术可以满足未来通信和AI/ML工作负载的需求，并具有易于访问的C或Python编程。该项目利用了美国和台湾的完整学术才能来影响半导体工程和教育。该奖项反映了NSF的法定任务，并使用基金会的知识分子优点和更广泛的影响审查标准，通过评估被认为是宝贵的支持。