SBIR Phase I: Atmospheric Pressure Deep Etch for MEMS Manufacturing and Integration

SBIR 第一阶段：用于 MEMS 制造和集成的大气压深蚀刻

• 批准号: 0839272
• 负责人: Simon Selitser
• 金额: $ 10万
• 依托单位: TimeDomain CVD Incorporated
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2009
• 资助国家: 美国
• 起止时间: 2009-01-01 至 2009-06-30
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=0839272&HistoricalAwards=false
• 关键词: SBIR; Phase; Atmospheric; Pressure; Deep

This Small Business Innovation Research (SBIR) Phase I project will develop a novel approach to through-wafer via formation in silicon. Vertical stacking of MEMS and CMOS devices is becoming increasingly popular for increasing functional density, and for combining specialized microelectromechanical systems (MEMS) with standard silicon integrated circuits. Vertical stacking generally requires that via holes for contacts be formed through a wafer using anisotropic etching, but current low-pressure techniques for performing this step are slow and expensive. This project will apply the company?s unique Linear Inductive Plasmatron technology to silicon etching using both the current multistep (etch/passivation) approach and single-step etching. The increased species densities at atmospheric pressure should enable passivation and etching of high-aspect-ratio features without etch-stop behavior observed at low pressure, and low electron temperatures ensure minimal plasma damage.If successful such a tool will greatly reduce the cost of via fabrication and enable 3D stacking of circuitry in applications where it would otherwise be prohibitively expensive. The unique characteristics of an atmospheric-pressure plasma etch process allow design of a processing tool that combines low cost, high throughput, and high performance. Because gas flows can be used to define reaction regions, wafers can be exposed to multiple process steps at high rates in batches using a carousel-type architecture. Once proven as a semiconductor manufacturing tool, the Linear Inductive Plasmatron is likely to find other applications in high-rate, low-cost processing for semiconductor fabrication, photovoltaic fabrication, and other manufacturing dependent on thin film deposition and etch processes.

这个小型企业创新研究（SBIR）第一阶段项目将开发一种新的方法来形成硅中的晶片通孔。MEMS和CMOS器件的垂直堆叠由于增加功能密度以及将专用微机电系统（MEMS）与标准硅集成电路相结合而变得越来越流行。垂直堆叠通常需要使用各向异性蚀刻穿过晶片形成用于接触的通孔，但是用于执行该步骤的当前低压技术缓慢且昂贵。本项目将适用于本公司？其独特的线性感应等离子管技术可使用当前的多步（蚀刻/钝化）方法和单步蚀刻进行硅蚀刻。在大气压下增加的物种密度应该能够钝化和蚀刻的高深宽比的功能，而不会在低压下观察到蚀刻停止行为，低电子温度确保最小的等离子体damage.If成功，这样的工具将大大降低过孔制造的成本，并使3D堆叠电路的应用，否则将是非常昂贵的。大气压等离子体蚀刻工艺的独特特性允许结合低成本、高产量和高性能的处理工具的设计。因为气流可用于限定反应区域，所以晶片可使用转盘式架构以高速率分批暴露于多个工艺步骤。一旦被证明是一种半导体制造工具，线性电感等离子体管很可能会在半导体制造、光伏制造和其他依赖于薄膜沉积和蚀刻工艺的制造的高速率、低成本加工中找到其他应用。