CAREER: Programming Interfaces and Hardware Designs for a Polymorphic Multicore Cache Architecture

半导体行业已经遇到了瓶颈——芯片级的功率和冷却限制减缓了时钟频率的发展，迫使行业转而押注于多核，以提供节能性能和可扩展性。尽管多核趋势给应用程序开发人员带来了令人生畏的挑战，但它也创造了传统多芯片多处理器无法提供的新机会：片上通信和计算的相对成本的巨大变化使应用程序设计具有紧密耦合的线程和频繁的共享，这将证明传统多处理器中延迟和带宽的限制。不幸的是，当前的多核内存系统不灵活，不适合支持协调执行，因为它们没有为核心到核心通信或优化芯片上的数据放置提供直接的方法。此外，芯片内访问模式在不同的应用程序之间差别很大——没有放之四海而皆准的静态缓存架构。为了解决这些缺陷，该项目寻求开发一种多态多核缓存架构（PMCA）——一种模块化片上缓存设计，其中软件配置基本硬件机制，以提供适合特定工作负载的缓存架构。PMCA的概念将从三个方面展开：首先，PMCA？S架构界面和行为设计通过全系统、周期的精确仿真进行。其次，将研究基于FPGA的功能仿真的语言层结构、软件管理策略和PMCA虚拟化。第三，对各种设计的性能、面积和功率进行权衡。

The semiconductor industry has hit a wall - chip-level power and cooling constraints have slowed the march of clock frequency, forcing industry to instead bet on multicore to provide energy-efficient performance scalability. Although the multicore trend poses daunting challenges for application developers, it also creates new opportunities unavailable in traditional multi-chip multiprocessors: the drastic change in the relative costs of on-chip communication and computation enable application designs with tightly-coupled threads and frequent sharing that would prove latency- and bandwidth-prohibitive in traditional multiprocessors. Unfortunately, current multicore memory systems are inflexible and poorly-suited to support coordinated execution, as they provide no direct means for core-to-core communication or to optimize data placement on chip. Moreover, intra-chip access patterns vary drastically across applications - there is no one-size-fits-all static cache architecture. To address these deficiencies, this project seeks to develop a Polymorphic Multicore Cache Architecture (PMCA) - a modular on-chip cache design where software configures primitive hardware mechanisms to provide a cache architecture suited to a specific workload. The PMCA concept will be pursued along three fronts: First, PMCA?s architectural interface and behavioral design through a full system, cycle accurate simulation will be conducted. Second,language level constructs, software management policies, and virtualization of PMCA through FPGA based functional emulation will be investigated. Third, trade-offs in performance, area, and power for various designs will be examined.