CAREER: Programming Interfaces and Hardware Designs for a Polymorphic Multicore Cache Architecture

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The semiconductor industry has hit a wall - chip-level power and cooling constraints have slowed the march of clock frequency, forcing industry to instead bet on multicore to provide energy-efficient performance scalability. Although the multicore trend poses daunting challenges for application developers, it also creates new opportunities unavailable in traditional multi-chip multiprocessors: the drastic change in the relative costs of on-chip communication and computation enable application designs with tightly-coupled threads and frequent sharing that would prove latency- and bandwidth-prohibitive in traditional multiprocessors. Unfortunately, current multicore memory systems are inflexible and poorly-suited to support coordinated execution, as they provide no direct means for core-to-core communication or to optimize data placement on chip. Moreover, intra-chip access patterns vary drastically across applications - there is no one-size-fits-all static cache architecture. To address these deficiencies, this project seeks to develop a Polymorphic Multicore Cache Architecture (PMCA) - a modular on-chip cache design where software configures primitive hardware mechanisms to provide a cache architecture suited to a specific workload. The PMCA concept will be pursued along three fronts: First, PMCA?s architectural interface and behavioral design through a full system, cycle accurate simulation will be conducted. Second,language level constructs, software management policies, and virtualization of PMCA through FPGA based functional emulation will be investigated. Third, trade-offs in performance, area, and power for various designs will be examined.