CAREER: Programming Interfaces and Hardware Designs for a Polymorphic Multicore Cache Architecture

职业：多态多核缓存架构的编程接口和硬件设计

• 批准号: 0845157
• 负责人: Thomas Wenisch
• 金额: $ 40万
• 依托单位: Regents of the University of Michigan - Ann Arbor
• 依托单位国家: 美国
• 项目类别: Continuing Grant
• 财政年份: 2009
• 资助国家: 美国
• 起止时间: 2009-02-15 至 2015-01-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=0845157&HistoricalAwards=false
• 关键词: CAREER; Programming; Interfaces; Hardware; Designs

The semiconductor industry has hit a wall - chip-level power and cooling constraints have slowed the march of clock frequency, forcing industry to instead bet on multicore to provide energy-efficient performance scalability. Although the multicore trend poses daunting challenges for application developers, it also creates new opportunities unavailable in traditional multi-chip multiprocessors: the drastic change in the relative costs of on-chip communication and computation enable application designs with tightly-coupled threads and frequent sharing that would prove latency- and bandwidth-prohibitive in traditional multiprocessors. Unfortunately, current multicore memory systems are inflexible and poorly-suited to support coordinated execution, as they provide no direct means for core-to-core communication or to optimize data placement on chip. Moreover, intra-chip access patterns vary drastically across applications - there is no one-size-fits-all static cache architecture. To address these deficiencies, this project seeks to develop a Polymorphic Multicore Cache Architecture (PMCA) - a modular on-chip cache design where software configures primitive hardware mechanisms to provide a cache architecture suited to a specific workload. The PMCA concept will be pursued along three fronts: First, PMCA?s architectural interface and behavioral design through a full system, cycle accurate simulation will be conducted. Second,language level constructs, software management policies, and virtualization of PMCA through FPGA based functional emulation will be investigated. Third, trade-offs in performance, area, and power for various designs will be examined.

半导体行业已经遇到了瓶颈-芯片级的功率和冷却限制减缓了时钟频率的发展，迫使行业转而押注于多核，以提供节能的性能可扩展性。虽然多核趋势给应用程序开发人员带来了巨大的挑战，但它也创造了传统多芯片多处理器无法提供的新机遇：片上通信和计算的相对成本的急剧变化使应用程序设计具有紧密耦合的线程和频繁的共享，这将证明传统多处理器中的延迟和带宽过高。不幸的是，当前的多核存储器系统是不灵活的，并且不适合支持协调执行，因为它们没有提供用于核到核通信或优化芯片上的数据放置的直接手段。此外，芯片内访问模式在应用程序中变化很大-没有一个尺寸适合所有静态缓存架构。为了解决这些缺陷，该项目旨在开发一种多态多核缓存架构（PMCA）-一种模块化的片上缓存设计，其中软件配置原始硬件机制，以提供适合特定工作负载的缓存架构。将在沿着三个方面推行《预防和管理局》的概念：第一，《预防和管理局》？的架构接口和行为设计，通过一个完整的系统，周期精确的模拟将进行。其次，语言级结构，软件管理政策，并通过基于FPGA的功能仿真PMCA虚拟化将进行调查。第三，权衡性能，面积和功率的各种设计将被检查。