Design and Analysis of Parallel Cache-efficient Algorithms

并行高速缓存算法的设计与分析

• 批准号: 0850775
• 负责人: Vijaya Ramachandran
• 金额: --
• 依托单位: University of Texas at Austin
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2008
• 资助国家: 美国
• 起止时间: 2008-09-15 至 2010-02-28
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=0850775&HistoricalAwards=false
• 关键词: Design; Analysis; Parallel; Cache; efficient

Chip multiprocessors (i.e., multicores) are rapidly emerging as the dominant platform for computing. This computing environment features parallel computing with shared-memory and a hierarchy of caches. This research will develop parallel and cache-efficient algorithms for many important problems that can be used effectively on multicores. The outcome of this research will be a set of provably correct methods for the efficient use of multicores, which is of critical importance given the imminent reality of multicores on every desktop. These results will have broad applicability to all fields that rely on compute-intensive tasks.

芯片多处理器（即，多核）正迅速成为计算的主导平台。这种计算环境的特点是具有共享内存和缓存层次结构的并行计算。 这项研究将开发并行和高速缓存效率的算法，许多重要的问题，可以有效地用于多核。 这项研究的结果将是一套可证明正确的方法，用于有效地使用多核，这是至关重要的，因为每个桌面上的多核即将到来的现实。这些结果将具有广泛的适用性，依赖于计算密集型任务的所有领域。