SHF: Small: Lookahead Logic Circuits for Performance, Power, and Reliability

SHF：小型：前瞻逻辑电路的性能、功耗和可靠性

• 批准号: 0917226
• 负责人: Kartik Mohanram
• 金额: $ 38.03万
• 依托单位: William Marsh Rice University
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2009
• 资助国家: 美国
• 起止时间: 2009-09-15 至 2012-03-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=0917226&HistoricalAwards=false
• 关键词: SHF; Small; Lookahead; Logic; Circuits

Timing errors resulting from process variability, manufacturing defects, and aging effects in scaled CMOS technologies are an important failure mode that impact the reliability of multi-level control logic in commodity mainstream computer systems. This project makes a case for lookahead logic circuits based on the principles of prefix computation to address performance, reliability, and power challenges posed by timing errors in multi-level control logic. Lookahead logic circuits promise low-cost logic-only solutions that can be used to (i) increase performance and/or yield by reducing logic delay, (ii) improve logic circuit robustness to timing errors by masking them, (ii) lower power consumption by increasing the scope of aggressive dynamic voltage and frequency scaling, and (iv) enable more effective and targeted post-silicon debug and online wearout prediction. The research will formalize the principles of lookahead-based function decomposition and prefix-based computation for multi-level logic circuits, develop logic synthesis and design solutions for lookahead logic, and investigate its applications in the context of superscalar and multi-threaded processor design.A major impact of this research is to enable ubiquitous low-cost highly reliable computing, by expanding its reach to domains, where custom solutions are economically infeasible. An integrated outcome of this project is the development of a testbed and web-based resources to facilitate research in reliable system design. Through course development and collaborations with industrial partners, the research will contribute to education, community resource development and technology transfer to industry.

在按比例缩放的CMOS技术中，由工艺可变性、制造缺陷和老化效应引起的定时误差是影响商品主流计算机系统中的多级控制逻辑的可靠性的重要故障模式。该项目提出了一个基于前缀计算原理的前瞻逻辑电路的案例，以解决多级控制逻辑中时序误差带来的性能、可靠性和功耗挑战。前瞻逻辑电路承诺低成本的仅逻辑解决方案，其可用于（i）通过减少逻辑延迟来提高性能和/或产量，（ii）通过掩蔽时序误差来提高逻辑电路对时序误差的鲁棒性，（ii）通过增加积极的动态电压和频率缩放的范围来降低功耗，以及（iv）实现更有效和更有针对性的硅后调试和在线磨损预测。该研究将形式化基于lookahead的多级逻辑电路的函数分解和基于前缀的计算的原理，开发lookahead逻辑的逻辑综合和设计解决方案，并研究其在超标量和多线程处理器设计中的应用。定制解决方案在经济上不可行。该项目的一个综合成果是开发了一个试验平台和基于网络的资源，以促进可靠系统设计的研究。 通过课程开发和与工业合作伙伴的合作，研究将有助于教育，社区资源开发和技术转移到行业。