SHF: Small: Lookahead Logic Circuits for Performance, Power, and Reliability
SHF: Small: Lookahead Logic Circuits for Performance, Power, and Reliability
批准号:
0917226
负责人:
Kartik Mohanram
金额:
$38.03万
依托单位国家:
美国
项目类别:
Standard Grant
财政年份:
2009
资助国家:
美国
项目状态:
已结题
起止时间:
2009-09-15 至 2012-03-31
中文摘要
在商用主流计算机系统中,由工艺变异性、制造缺陷和老化效应引起的时序误差是影响多级控制逻辑可靠性的重要失效模式。该项目提出了基于前缀计算原理的前瞻性逻辑电路的案例,以解决多级控制逻辑中时序错误带来的性能,可靠性和功耗挑战。前瞻性逻辑电路承诺低成本的纯逻辑解决方案,可用于(i)通过减少逻辑延迟来提高性能和/或产量,(ii)通过屏蔽时序错误来提高逻辑电路的鲁棒性,(ii)通过增加积极的动态电压和频率缩放范围来降低功耗,以及(iv)实现更有效和有针对性的后硅调试和在线磨损预测。研究将形式化多层级逻辑电路中基于前瞻的功能分解和基于前缀的计算原理,开发前瞻逻辑的逻辑综合和设计方案,并研究其在超标量和多线程处理器设计中的应用。这项研究的一个主要影响是通过将其范围扩展到定制解决方案在经济上不可行的领域,使无处不在的低成本高可靠计算成为可能。该项目的一个综合成果是开发一个试验台和基于网络的资源,以促进可靠系统设计的研究。通过课程开发和与工业伙伴的合作,研究将有助于教育、社区资源开发和技术向工业转移。
英文摘要
Timing errors resulting from process variability, manufacturing defects, and aging effects in scaled CMOS technologies are an important failure mode that impact the reliability of multi-level control logic in commodity mainstream computer systems. This project makes a case for lookahead logic circuits based on the principles of prefix computation to address performance, reliability, and power challenges posed by timing errors in multi-level control logic. Lookahead logic circuits promise low-cost logic-only solutions that can be used to (i) increase performance and/or yield by reducing logic delay, (ii) improve logic circuit robustness to timing errors by masking them, (ii) lower power consumption by increasing the scope of aggressive dynamic voltage and frequency scaling, and (iv) enable more effective and targeted post-silicon debug and online wearout prediction. The research will formalize the principles of lookahead-based function decomposition and prefix-based computation for multi-level logic circuits, develop logic synthesis and design solutions for lookahead logic, and investigate its applications in the context of superscalar and multi-threaded processor design.A major impact of this research is to enable ubiquitous low-cost highly reliable computing, by expanding its reach to domains, where custom solutions are economically infeasible. An integrated outcome of this project is the development of a testbed and web-based resources to facilitate research in reliable system design. Through course development and collaborations with industrial partners, the research will contribute to education, community resource development and technology transfer to industry.
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