TC: Medium: Collaborative Research: Side-Channel-Proof Embedded Processors with Integrated Multi-Layer Protection

摘要：具有集成多层保护的防侧通道嵌入式处理器嵌入式数字系统无处不在，可能包含敏感信息，如果落入不法分子手中，这些信息可能会被用于恶意目的。因此，强大的加密算法被整合到这些设备中。然而，攻击者已经将他们的目标从密码算法本身切换到这些算法的硬件/软件实现上，通过侧通道？芯片尺寸。从硬件的角度来看，这种侧通道攻击可以在电路级和架构级实现。虽然已经进行了大量的研究来缓解侧信道攻击，但这些解决方案缺乏灵活性、缺乏系统性，并且开销较高。本研究的目标是开发一种通用的解决方案，将架构级和电路级对抗措施协同结合起来，以减轻所有主要类别的旁路攻击，从而产生极其安全、高度灵活、低开销的数字系统设计方法。在这个概念验证项目中，将在两个层面上进行初步研究。在架构级，将开发新的架构支持，以缓解架构级计时和访问驱动的攻击。在电路级，将利用延迟不敏感的三值逻辑来设计新的体系结构支持以及与MIPS32 4K兼容的嵌入式微处理器的其他关键组件。将在体系结构级和电路级评估侧信道攻击抵抗的有效性和效率。将开发电路级和架构级攻击缓解的教育模块。研究生和本科生，特别是来自代表人数不足的群体的学生，将参与这个项目。研究成果将通过期刊文章、会议报告和适当的网站向学术界和工业界传播。

Abstract: Side-Channel-Proof Embedded Processors with Integrated Multi-Layer ProtectionEmbedded digital systems are ubiquitous and may contain sensitive information that could be used for malicious purposes if fallen into the wrong hands. Therefore, strong cryptographic algorithms have been incorporated inside these devices. However, attackers have switched their targets from the cryptographic algorithms themselves to the hardware/software implementations of these algorithms, through ?side-channel? chip measurements. From a hardware perspective, such side-channel attacks can be implemented at both the circuit-level and architecture-level. Although much research has been performed in mitigating side-channel attacks, these solutions are inflexible, unsystematic, and have high overhead. The goal of this research is to develop a universal solution that synergistically combines both architecture-level and circuit-level countermeasures for mitigating all major categories of side-channel attacks, to yield an extremely secure, highly flexible, low overhead digital system design methodology. In this proof-of-concept project, preliminary research will be carried out at both levels. At the architecture-level, novel architectural support to mitigate architecture-level timing and access-driven attacks will be developed. At the circuit-level, Delay-Insensitive Ternary Logic will be utilized to design the new architectural support as well as other key components of a MIPS32 4K-compatible embedded microprocessor. The effectiveness and efficiency of side-channel attack resistance at both architecture-level and circuit-level will be evaluated. Educational modules of circuit-level and architecture-level attack mitigation will be developed. Graduate and undergraduate students, especially from underrepresented groups, will be involved in this project. The research outcome will be disseminated to the academic and industrial communities through journal articles, conference presentations, and appropriate websites.