SaTC: CORE: Small: Towards Smart and Secure Non Volatile Memory

非易失性存储器（NVM）技术和3D集成技术重塑了存储器系统。尽管NVM提供了许多理想的特性，例如低泄漏功率和快速系统重启，但NVM的非易失性引入了对数据残留攻击的脆弱性。该项目利用垂直堆叠的3D集成电路实现的内存处理（PIM）来克服与NVM相关的安全挑战。在该项目中，我们使用了一种攻击模型，其中攻击者可以物理地获得NVM芯片并扫描存储在NVM中的数据，还可以窥探存储器总线以获取数据和地址;并且可以篡改存储器内容以及命令。我们的信任基础包括处理器和内存芯片，这意味着芯片内的硬件逻辑和状态寄存器对攻击者来说是隐藏的。为了防止数据扫描和内存总线窥探，我们利用计数器模式加密来加密数据和混淆地址。存储在NVM中的数据总是加密的，而地址在处理器侧加密并在存储器侧解密。解密逻辑成为NVM芯片上的PIM逻辑的一部分。为了防止数据篡改，我们开发了有效的完整性检查，重新利用纠错码（ECC）的完整性检查，使现有的纠错逻辑可以用于错误检测/纠正和完整性验证。总的来说，我们利用PIM来保护数据和访问模式，并确保数据的完整性。该项目的最终结果是智能和安全的NVM架构设计。

Non-volatile memory (NVM) technologies and the 3D-integration technology reshape memory systems. Although providing many desirable features such as low leakage power and fast system restart, the non-volatility of NVM introduces the vulnerability to data remanence attacks. This project leverages the processing-in-memory (PIM), enabled by vertically stacked 3D integration of integrated circuits, to overcome the security challenge associated with NVM.In this project, we use an attack model, in which an attacker can physically obtain the NVM chip and scan the data stored in NVM, can also snoop on the memory bus to retrieve data and addresses; and can tamper with the memory content as well as commands. Our trust base includes both the processor and the memory chip, meaning that the hardware logic and state registers inside the chips are well hidden from the attacker. To protect against data scanning and memory bus snooping, we utilize counter-mode encryption to encrypt data and obfuscate addresses. The data stored in NVM are always encrypted while the addresses are encrypted at the processor side and decrypted at the memory side. The decryption logic becomes a part of the PIM logic on NVM chips. To protect against data tampering, we develop efficient integrity checks by re-purposing error correction codes (ECC) for integrity checking such that the existing error correction logic can be used for both error detection/correction and integrity verification. Overall, we leverage PIM to protect data and access patterns and ensure the data integrity. The end result of the project is smart and secure NVM architecture designs.